W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 158
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W83697HFFDC
Manufacturer Part Number
W83697HFFDC
Description
LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
Manufacturer
Information Storage Devices, Inc
Datasheet
1.W83697HFFDC.pdf
(167 pages)
- Current page: 158 of 167
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CR70 (Default 0x09 if PNPCSV = 0 during POR, default 0x00 otherwise)
CRF0 (GP5 selection register. Default 0xFF)
CRF1 (GP5 data register. Default 0x00)
CRF2 (GP5 inversion register. Default 0x00)
CRF3 (PLED mode register. Default 0x00)
When set to a '1', the incoming/outgoing port value is inverted.
When set to a '0', the incoming/outgoing port value is the same as in data register.
When set to a '1', respective GPIO port is programmed as an input port.
If a port is programmed to be an output port, then its respective bit can be read/written.
When set to a '0', respective GPIO port is programmed as an output port.
If a port is programmed to be an input port, then its respective bit can only be read.
Bit 7 - 4 : Reserved.
Bit [3:0] : These bits select IRQ resource for MIDI Port .
Bit 7 ~ 3 : Reserved .
Bit 2
Bit 1 ~ 0 : select PLED mode
: select WDTO count mode.
= 0
= 1
= 00 Power LED pin is tri-stated.
= 01 Power LED pin is droved low.
= 10 Power LED pin is a 1Hz toggle pulse with 50 duty cycle.
= 11 Power LED pin is a 1/4Hz toggle pulse with 50 duty cycle.
second
minute
- 149 -
Publication Release Date: Feb. 2002
W83697HF/F
Revision 0.70
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