W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 147

• Manufacturer Part Number: W83697HFFDC
• Description: LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
• Manufacturer: Information Storage Devices, Inc

CR26 (Default 0x00)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
: SEL4FDD
= 0
= 1
: HEFRAS
These two bits define how to enable Configuration mode. The corresponding power-on
setting pin is RTSA #(pin 49).
HEFRAS Address and Value
= 0
= 1
: LOCKREG
= 0
= 1
: Reserved
: DSFDLGRQ
= 0
= 1
: DSPRLGRQ
= 0
= 1
: DSUALGRQ
= 0
= 1
: DSUBLGRQ
= 0
= 1
Select two FDD mode.
Select four FDD mode
Write 87h to the location 2E twice.
Write 87h to the location 4Etwice.
Enable R/W Configuration Registers.
Disable R/W Configuration Registers.
Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is
effective on selecting IRQ
Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not
effective on selecting IRQ
Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on
selecting IRQ
Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective
on selecting IRQ
Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
IRQ
Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on
selecting IRQ
Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
IRQ
Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on
selecting IRQ
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Publication Release Date: Feb. 2002
W83697HF/F
Revision 0.70