W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 15

• Manufacturer Part Number: W83697HFFDC
• Description: LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
• Manufacturer: Information Storage Devices, Inc

1. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details.
I/O 8t
I/O 12t
I/O 12tp3
I/OD 12t
I/O 24t
OUT 12t
OUT 12tp3
OD 12
OD 24
IN cs
IN t
IN td
IN ts
IN tsp3
1.1 LPC Interface
CLKIN
PME#
PCICLK
LDRQ#
SERIRQ
LAD[3:0]
LFRAME#
LRESET#
SYMBOL
- TTL level bi-directional pin with 8 mA source-sink capability
- TTL level bi-directional pin with 12 mA source-sink capability
- 3.3V TTL level bi-directional pin with 12 mA source-sink capability
- TTL level bi-directional pin open drain output with 12 mA sink capability
- TTL level bi-directional pin with 24 mA source-sink capability
- TTL level output pin with 12 mA source-sink capability
- 3.3V TTL level output pin with 12 mA source-sink capability
- Open-drain output pin with 12 mA sink capability
- Open-drain output pin with 24 mA sink capability
- CMOS level Schmitt-trigger input pin
- TTL level input pin
- TTL level input pin with internal pull down resistor
- TTL level Schmitt-trigger input pin
- 3.3V TTL level Schmitt-trigger input pin
23-26
PIN
17
98
19
20
21
27
28
I/O
I/OD
O
IN
IN
IN
OD
I/O
12tp3
IN
tsp3
12tp3
tsp3
tsp3
12
t
12t
System clock input. According to the input frequency 24MHz or
48MHz, it is selectable through register. Default is 24MHz input.
Generated PME event.
PCI clock input.
Encoded DMA Request signal.
Serial IRQ input/Output.
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
Indicates start of a new cycle or termination of a broken cycle.
Reset signal. It can connect to PCIRST# signal on the host.
- 6 -
FUNCTION
Publication Release Date:Feb. 2002
W83697HF
Revision 0.70