aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 92

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
Table 101. SPICON MMR Bit Designations
Bit
15 to 14
13
12
11
10
9
8
7
6
5
4
3
2
Name
SPIMDE
SPITFLH
SPIRFLH
SPICONT
SPILP
SPIOEN
SPIROW
SPIZEN
SPITMDE
SPILF
SPIWOM
SPICPO
SPICPH
Description
SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.
[00] = Tx interrupt occurs when 1 byte has been transferred. Rx interrupt occurs when 1 or more bytes have been
received into the FIFO.
[01] = Tx interrupt occurs when 2 bytes has been transferred. Rx interrupt occurs when 1 or more bytes have been
received into the FIFO.
[10] = Tx interrupt occurs when 3 bytes has been transferred. Rx interrupt occurs when 3 or more bytes have been
received into the FIFO.
[11] = Tx interrupt occurs when 4 bytes has been transferred. Rx interrupt occurs when the Rx FIFO is full, or 4 bytes
present.
SPI Tx FIFO Flush enable bit.
Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required.
If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit.
Any writes to the Tx FIFO are ignored while this bit is set.
Clear this bit to disable Tx FIFO flushing.
SPI Rx FIFO Flush enable bit.
Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required.
If this bit is set all incoming data is ignored and no interrupts are generated.
If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer.
Clear this bit to disable Rx FIFO flushing.
Continuous Transfer Enable.
Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the
Tx register. .SS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty.
Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer.
If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of 1 serial clock cycle.
Loop Back Enable bit.
Set by user to connect MISO to MOSI and test software.
Cleared by user to be in normal mode.
Slave MISO Output enable bit.
Set this bit for MISO to operate as normal.
Clear this bit to disable the output driver on the MISO pin. The MISO pin is Open-Drain when this bit is clear.
SPIRX Overflow Overwrite Enable.
Set by user, the valid data in the Rx register is overwritten by the new serial byte received.
Cleared by user, the new serial byte received is discarded.
SPI transmit Zeros when Tx FIFO is empty.
SPI Transfer and Interrupt Mode.
LSB First Transfer Enable Bit.
SPI Wired Or Mode enable bit
Set to 1 enable Open Drain data Output enable. External pull-ups required on data out pins.
Clear for normal output levels.
Serial Clock Polarity Mode Bit.
Set by user, the serial clock idles high.
Serial Clock Phase Mode Bit.
Set by user to initiate transfer with a write to the SPITX register. Interrupt only occurs when Tx is empty.
Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when Rx is full.
Set this bit to transmit “0x00” when there is no valid data in the Tx FIFO.
Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO.
Set by user, the LSB is transmitted first.
Cleared by user, the MSB is transmitted first.
Cleared by user, the serial clock idles low.
Set by user, the serial clock pulses at the beginning of each serial bit transfer.
Cleared by user, the serial clock pulses at the end of each serial bit transfer.
Rev. PrA | Page 92 of 100
Preliminary Technical Data