aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 87

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Bit
4
3
2
1
0
Name
I2CSRxFO
I2CSRXQ
I2CSTXQ
I2CSTFE
I2CETSTA
Description
Slave Rx FIFO Overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
I
This bit is set to 1 when the Rx FIFO of the slave is not empty.
This bit causes an interrupt to occur if the I2CSRXENI bit in I2CSCON is set.
The Rx FIFO must be read or flushed to clear this bit.
I
This bit is set to 1 when the slave receives a matching address followed by a read.
If the I2CSETEN bit in I2CSCON is =0, , this bit goes high just after the negative edge of SCL during the read bit
transmission.
If the I2CSETEN bit in I2CSCON is =1, this bit goes high just after the positive edge of SCL during the Read bit
transmission.
This bit causes an interrupt to occur if the I2CSTXENI bit in I2CSCON is set.
This bit is cleared in all other conditions.
I
This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at the
rising edge of SCL during the Read bit.
This bit is cleared in all other conditions.
I
If the I2CSETEN bit in I2CSCON is =0, this bit goes high of the slave Tx FIFO is empty.
If the I2CSETEN bit in I2CSCON is =1, this bit goes high just after the positive edge of SCL during the Write bit
transmission.
This bit asserts once only for a transfer.
This bit is cleared after being read.
2
2
2
2
C Slave Receive Request bit.
C Slave Transmit Request bit
C Slave FIFO underflow Status bit
C Slave Early Transmit FIFO Status bit
Rev. PrA | Page 87 of 100
ADuC7060/ADuC7061/ADuC7062