aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 77

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
UART Control Register 1
This 8-bit register controls the operation of the UART in
conjunction with COMCON0.
Name:
Address:
Default value:
Access:
UART Status Register 0
Name:
Address:
Default value:
Access:
Function:
Table 86. COMSTA0 MMR Bit Designations
Bit
7
6
5
4
3
2
1
0
COMCON1
0x00
Read/write
0xFFFF0710
COMSTA0
0xFFFF0714
0x60
Read only
This 8-bit read-only register reflects the current status on the UART.
Name
TEMT
THRE
BI
FE
PE
OE
DR
Description
Reserved.
COMTX and Shift Register Empty Status Bit.
Set automatically if COMTX and the shift register are empty. This bit indicates that the data has
been transmitted, that is, no more data is present in the shift register.
Cleared automatically when writing to COMTX.
COMTX Empty Status Bit.
Set automatically if COMTX is empty. COMTX can be written as soon as this bit is set, the previous
data might not have been transmitted yet and can still be present in the shift register.
Cleared automatically when writing to COMTX.
Break Indicator.
Set when SIN is held low for more than the maximum word length.
Cleared automatically.
Framing Error.
Set when the stop bit is invalid.
Cleared automatically.
Parity Error.
Set when a parity error occurs.
Cleared automatically.
Overrun Error.
Set automatically if data are overwritten before being read.
Cleared automatically.
Data Ready.
Set automatically when COMRX is full.
Cleared by reading COMRX.
Rev. PrA | Page 77 of 100
Table 85. COMCON1 MMR Bit Designations
Bit
7:5
4
3:2
1
0
Name
LOOPBACK
RTS
DTR
ADuC7060/ADuC7061/ADuC7062
Description
Reserved bits. Not used.
Loopback. Set by user to enable
loopback mode. In loopback mode,
the TxD is forced high.
Reserved bits. Not used.
Request to Send.
Set by user to force the RTS output to 0.
Cleared by user to force the RTS
output to 1.
Data Terminal Ready.
Set by user to force the DTR output to 0.
Cleared by user to force the DTR
output to 1.