aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 43

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Auxiliary Channel Gain Calibration Register
Name:
Address:
Default Value:
Access:
Function:
Table 45. ADC1GAIN MMR Bit Designations
Bits
15 to 0
Primary Channel ADC Result Counter Limit Register
Name:
Address:
Default Value:
Access:
Function:
Table 46. ADC0RCR MMR Bit Designations
Bits
15 to 0
Primary Channel ADC Result Count Register
Name:
Address:
Default Value:
Access:
Function:
Table 47. ADCORCV MMR Bit Designations
Bits
15 to 0
Description
ADC1 16-bit Calibration Gain Value.
Description
ADC0 Result Counter Limit/Re-Load register.
Description
ADC0 Result Counter register.
ADC1GAIN
0xFFFF0530
Part specific, factory programmed
Read/write
This gain MMR holds a 16-bit gain calibration coefficient for scaling an Auxiliary channel conversion result. The
register is configured at power-on with a factory default value. However, this register is automatically overwritten if a
gain calibration of the Auxiliary channel is initiated by the user via bits in the ADCMDE MMR. User code can only
write to this calibration register if the ADC is in idle mode. An ADC must be enabled and in idle mode before being
written to any offset or gain register. The ADC must be in idle mode for at least 23 μs.
ADCORCR
0xFFFF0534
0x0001
Read/write
This 16-bit MMR sets the number of conversions required before an ADC interrupt is generated. By default, this
register is set to 0x01. The ADC counter function must be enabled via the ADC result counter enable bit in the
ADCCFG MMR.
ADCORCV
0xFFFF0538
0x0000
Read only
This 16-bit, read only MMR holds the current number of primary ADC conversion results. It is used in conjunction
with ADC0RCR to mask Primary channel ADC interrupts, generating a lower interrupt rate. When ADC0RCV =
ADC0RCR, the value in ADC0RCV resets to 0 and recommences counting. It can also be used in conjunction with the
accumulator (ADC0ACC) to allow an average calculation to be undertaken. The result counter is enabled via
ADCCFG[0]. This MMR is also reset to 0 when the Primary-ADC is reconfigured, that is, when the ADC0CON or
ADCMDE are written.
Rev. PrA | Page 43 of 100
ADuC7060/ADuC7061/ADuC7062