aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 21

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
COMPLETE MMR LISTING
In the following MMR tables, addresses are listed in hex code. Access types include R for read, W for write, and RW for read and write.
Table 11. IRQ Address Base = 0xFFFF0000
Address
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0100
0x0104
0x0108
0x010C
0x011C
0x013C
Table 12. System Control Address Base = 0xFFFF0200
Address
0x0220
0x0230
0x0234
1
Updated by kernel.
Name
IRQSTA
IRQSIG
IRQEN
IRQCLR
SWICFG
IRQBASE
IRQVEC
IRQP0
IRQP1
IRQP2
RESERVED
IRQCONN
IRQCONE
IRQCLRE
IRQSTAN
FIQSTA
FIQSIG
FIQEN
FIQCLR
FIQVEC
FIQSTAN
Name
REMAP
RSTSTA
RSTCLR
1
Byte
1
1
1
Access
Type
R/W
R/W
W
Byte
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Access
Type
R
R
RW
W
W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
RW
W
R
R
Default Value
0x00
0x01
0x00
Default
Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Rev. PrA | Page 21 of 100
Description
REMAP Control Register. See the Remap Operation section.
RSTSTA Status MMR. See the Reset section.
RSTCLR MMR for clearing RSTSTA register.
Current State of All IRQ Sources (Enabled and Disabled).
Enabled IRQ Sources.
MMR to Disable IRQ Sources.
Base Address of all Vectors. Points to start of 64-byte memory block
which can contain up to 32 pointers to separate subroutine handlers.
This register contains the subroutine address for the currently active IRQ
source.
Contains the interrupt priority setting for interrupt Source 1 to Source 7.
An interrupt can have a priority setting of 0 to 7. For example:
Contains the interrupt priority setting for Interrupt Source 8 to Interrupt
Source 15. For example:
Contains the interrupt priority setting for Interrupt Source 16 to Interrupt
Source 19.
Reserved.
Used to enable IRQ and FIQ interrupt nesting.
Configures the external interrupt sources as either rising edge, falling
edge, or level triggered.
Used to clear an edge level triggered interrupt source.
This register indicates the priority level of an interrupt that has just
caused an interrupt exception.
Current State of All FIQ Sources (Enabled and Disabled).
Enabled FIQ Sources.
MMR to Disable FIQ Sources.
FIQ Interrupt Vector.
Indicates the priority level of an FIQ that has just caused an FIQ
exception.
Description
Active IRQ Source.
Software Interrupt Configuration MMR.
Bits[7:4] containthe priority level for Interrupt 1.
Bits[11:8] contain the priority level for Interrupt 2.
Bits[31:28] contain the priority level for Interrupt 7.
Bits[7:4] contain the priority level for Interrupt 9.
Bits[11:8] contain the priority level for Interrupt 10.
Bits[31:28] contain the priority level for Interrupt 15.
Active FIQ Source.
ADuC7060/ADuC7061/ADuC7062