aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 39

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Bit
7
6 to 0
1
2
Table 37. ADC Conversion Rates and Settling Times
Chop
Enabled
No
No
No
No
Yes
1
Table 38. Allowable Combinations of SF and AF
SF
0 to 31
32 to 63
64 to 127
Due to limitations on the digital filter internal data path, there are some limitations on the combinations of the Sinc3 decimation factor (SF) and averaging factor (AF)
that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in lower power mode.
In low power mode and low power plus mode, the ADC is driven directly by the low power oscillator (131 kHz) and not 512 kHz. All f
by 4 (approx).
An additional time of approximately 60 μs per ADC is required before the first ADC is available.
Name
NOTCH2
SF[6:0]
Averaging Factor
No
No
Yes
Yes
N/A
Description
Sinc3 Modify. Set by the user to modify the standard Sinc3 frequency response to increase the filter stop band
rejection by approximately 5 dB. This is achieved by inserting a second notch (NOTCH2) at
where f
Sinc3 Decimation Factor (SF)
Sinc3 filter. The output rate from the Sinc3 filter is given by
when the chop bit (Bit 15, chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125.
For SF = 126, f
For SF = 127, f
For information on calculating the f
f
f
NOTCH2
ADC
NOTCH
= (512,000/([SF+1] × 64)) Hz
0
Yes
Yes
Yes
= 1.333 × f
is the location of the first notch in the response.
Running
Average
No
Yes
No
Yes
N/A
ADC
ADC
is forced to 60 Hz.
is forced to 50 Hz.
NOTCH
1
f
.The value (SF) written in these bits controls the oversampling (decimation factor) of the
[
[
[
[
[
ADC
SF
SF
SF
SF
SF
1 to 7
Yes
Yes
No
512
512
Normal Mode
+
+
+
+
+
] 1
,
] 1
,
] 1
] 1
] 1
000
000
512
512
2
×
×
×
×
×
512
ADC
Rev. PrA | Page 39 of 100
64
64
64
64
64
,
,
000
000
×
for SF (other than 126 and 127) and AF values, refer to Table X.
×
×
,
000
3 [
3 [
3 [
+
+
+
AF
AF
AF
8 to 63
Yes
No
No
]
]
]
+
3
f
AF Range
[
[
[
[
[
ADC
SF
SF
SF
SF
SF
131
131
Low Power Mode
+
+
+
+
+
] 1
] 1
] 1
,
,
] 1
] 1
ADuC7060/ADuC7061/ADuC7062
072
072
131
131
×
×
×
×
×
131
64
64
64
,
64
64
,
072
072
×
×
×
,
072
3 [
3 [
3 [
+
+
+
AF
AF
AF
]
]
]
+
3
ADC
calculations should be divided
t
SETTLING
f
f
f
f
f
ADC
ADC
ADC
ADC
ADC
1
2
2
3
4
1