aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 62

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
Timer0 Capture Register
Name:
Address:
Default value:
Access:
Function:
Timer0 Control Register
Name:
Address:
Default value:
Access:
Function:
Table 74. T0CON MMR Bit Designations
Bit
31 to 24
23
22 to 20
19
18
17
16 to 12
11
10 to 9
8
7
6
Name
T0PEN
T0PCF
T0SRCI
T0CAPEN
T0CAPSEL
T0DIR
T0EN
T0MOD
T0PVAL
T0CLKSEL
T0CAP
0xFFFF0330
0x00000000
Read only
This 32-bit register holds the 32-bit value captured by an enabled IRQ event.
T0CON
0xFFFF0328
0x01000000
Read/write
This 32-bit MMR configures the mode of operation of Timer0.
Description
8-Bit Postscaler.
By writing to these eight bits, a value is written to the postscaler. Writing 0 is interpreted as a 1.
By reading these eight bits, the current value of the counter is read.
Timer0 Enable Postscaler.
Set to enable the Timer0 postscaler. If enabled, interrupts are generated after T0CON[31:24] periods
Cleared to disable the Timer0 postscaler.
Reserved. These bits are reserved and should be written as 0 by user code.
Postscaler Compare Flag. Read only. Set if the number of Timer0 overflows is equal to the number written
to the postscaler.
Timer0 Interrupt Source.
Set to select interrupt generation from the postscaler counter.
Cleared to select interrupt generation directly from Timer0.
Event Enable Bit.
Set by user to enable time capture of an event.
Cleared by user to disable time capture of an event.
Event select Bits[0:31]. The events are described in (Table TBD).
Reserved bit.
Clock Select.
00 = 32.768 kHz
01 = 10.24 MHz/CD
10 = 10.24 MHz
11 = P1.0
Count Up.
Set by user for Timer0 to count up.
Cleared by user for Timer0 to count down (default).
Timer0 Enable Bit.
Set by user to enable Timer0.
Cleared by user to disable Timer0 (default).
Timer0 Mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode (default).
as defined by T0LD.
Rev. PrA | Page 62 of 100
Preliminary Technical Data