aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 57

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
IRQCONN Register
The IRQCONN register is the IRQ and FIQ control register. It
contains two active bits. The first to enable nesting and
prioritization of IRQ interrupts the other to enable nesting and
prioritization of FIQ interrupts.
If these bits are cleared, then FIQs and IRQs may still be used
but it is not possible to nest IRQs or FIQs. Neither is it possible
to set an interrupt source priority level. In this default state, an
FIQ does have a higher priority than an IRQ.
Name:
Address:
Default value:
Access:
Table 67. IRQCONN MMR Bit Designations
Bit
31:2
1
0
IRQSTAN Register
If IRQCONN.0 is asserted and IRQVEC is read then one of
these bits is asserted. The bit that asserts depend on the priority
of the IRQ. If the IRQ is of Priority 0 then Bit 0 asserts, Priority 1
then Bit 1 asserts, and so forth. When a bit is set in this register,
all interrupts of that priority and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09 then writing 0xFF changes
the register to 0x08, and writing 0xFF a second time changes
the register to 0x00.
Name:
Address:
Default value:
Access:
Table 68. IRQSTAN MMR Bit Designations
Bit
31:8
7:0
Name
Reserved
ENFIQN
ENIRQN
Name
Reserved
Description
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
Setting this bit to 1 enables nesting of IRQ
interrupts. Clearing this bit means no nesting
or prioritization of IRQs is allowed.
Description
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit, means no nesting
or prioritization of FIQs is allowed.
IRQCONN
0xFFFF0030
0x00000000
Read and write
IRQSTAN
0xFFFF003C
0x00000000
Read and write
Rev. PrA | Page 57 of 100
FIQVEC Register
The FIQ interrupt vector register, FIQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active FIQ. This register should only be read when
an FIQ occurs and FIQ interrupt nesting has been enabled by
setting Bit 1 of the IRQCONN register.
Name:
Address:
Default value:
Access:
Table 69. FIQVEC MMR Bit Designations
Bit
31:23
22:7
6:2
1:0
FIQSTAN Register
If IRQCONN.1 is asserted and FIQVEC is read then one of
these bits assert. The bit that asserts depends on the priority of
the FIQ. If the FIQ is of Priority 0 then Bit 0 asserts, Priority 1
then Bit 1 asserts, and so forth.
When a bit is set in this register all interrupts of that priority
and lower are blocked.
To clear a bit in this register all bits of a higher priority must be
cleared first. It is only possible to clear one bit as a time. For
example if this register is set to 0x09 then writing 0xFF changes
the register to 0x08 and writing 0xFF a second time changes the
register to 0x00.
Name:
Address:
Default value:
Access:
Table 70. FIQSTAN MMR Bit Designations
Bit
31:8
7:0
Name
Reserved
Type
Read only
R/W
Reserved
ADuC7060/ADuC7061/ADuC7062
Description
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit, means no nesting
or prioritization of FIQs is allowed.
Initial
Value
0
0
0
0
FIQVEC
0xFFFF011C
0x00000000
Read only
FIQSTAN
0xFFFF013C
0x00000000
Read and write
Description
Always read as 0.
IRQBASE register value.
Highest PriorityFIQ Source. This is
a value between 0 to 19 represent
the possible interrupt sources. For
example, if the highest currently
active FIQ is Timer 1, then these
bits are [01000].
Reserved bits.