aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 34

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

ADuC7060/ADuC7061/ADuC7062
Bit
4
3
2
1
0
ADC Interrupt Mask Register
Name:
Address:
Default value:
Access:
Function:
Table 33. ADCMSKI MMR Bit Designations
Bit
7
6
5
4
3
2
1
0
Name
ADC0ATHEX_INTEN
ADC0THEX_INTEN
ADC0OVR_INTEN
ADC1RDY_INTEN
ADC0RDY_INTEN
Name
ADC0THEX
ADC0OVR
ADC1RDY
ADC0RDY
ADCMSKI
0xFFFF0504
0x00
Read/write
This register allows the ADC interrupt sources to be enabled individually. The bit positions in this register are the
same as the lower eight bits in the ADCSTA MMR. If a bit is set by user code to a 1, the respective interrupt is enabled.
By default, all bits are 0, meaning all ADC interrupt sources are disabled.
Description
Primary Channel ADC Comparator Threshold. This bit is only valid if the primary channel ADC comparator is
enabled via the ADCCFG MMR.
This bit is set by hardware if the absolute value of the primary ADC conversion result exceeds the value written in
the ADC0TH MMR. If the ADC threshold counter is used (ADC0TCL), this bit is only set when the specified number
of primary ADC conversions equals the value in the ADC0THV MMR.
Other wise, this bit is clear.
Primary Channel ADC Overrange Bit. If the overrange detect function is enabled via the ADCCFG MMR, this bit is
set by hardware if the Primary-ADC input is grossly (>30% approximate) overrange. This bit is updated every
125 μs. After it is set, this bit can only be cleared by software when ADCCFG[2] is cleared to disable the function, or
the ADC gain is changed via the ADC0CON MMR.
Not Used. These bits are reserved for future functionality and should not be monitored by user code.
Auxiliary ADC Result Ready bit.
If the Auxiliary channel ADC is enabled, this bit is set by hardware as soon as a valid conversion result is written in
the ADC1DAT MMR. It is also set at the end of a calibration sequence.
This bit is cleared by reading ADC1DAT followed by reading ADC0DAT. ADC0DAT must be read to clear this bit,
even if the primary ADC is not enabled.
Primary ADCResult Ready bit.
If the primary channel ADC is enabled, this bit is set by hardware as soon as a valid conversion result is written in
the ADC0DAT MMR. It is also set at the end of a calibration sequence.
This bit is cleared by reading ADC0DAT.
When set to 1, this bit enables an interrupt when the ADC0OVR bit in the ADCSTA register is set.
Description
Not Used. These bits are reserved for future functionality and should not be monitored by user code.
ADC0 Accumulator Comparator Threshold Exceeded Interrupt Enable Bit.
When set to 1, this bit enables an interrupt when the ADC0ATHEX bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
Not Used. These bits are reserved for future functionality and should not be monitored by user code.
Primary Channel ADC Comparator Threshold Exceeded Interrupt Enable Bit.
When set to 1, this bit enables an interrupt when the ADC0THEX bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
When this bit is cleared, this interrupt source is disabled.
Not Used. These bits are reserved for future functionality and should not be monitored by user code..
Auxiliary ADC Result Ready Bit.
When set to 1, this bit enables an interrupt when the ADC1RDY bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
Primary ADC Result Ready Bit.
When set to 1, this bit enables an interrupt when the ADC0RDY bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
Rev. PrA | Page 34 of 100
Preliminary Technical Data