aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 17
aduc7062
Manufacturer Part Number
aduc7062
Description
Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADUC7062.pdf
(100 pages)
Preliminary Technical Data
ARM code can run directly from SRAM at full clock speed
given that the SRAM array is configured as a 32-bit wide
memory array. SRAM is read/writeable in 8-, 16-, and 32-bit
segments.
Remap
The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020.
By default, after a reset, the Flash/EE memory is logically
mapped to Address 0x00000000.
It is possible to logically remap the SRAM to Address 0x00000000
by setting Bit 0 of the SYSMAP0 MMR located at 0xFFFF0220.
To revert Flash/EE to 0x00000000, Bit 0 of REMAP is cleared.
It is sometimes desirable to remap RAM to 0x00000000 to
optimize the interrupt latency of the ADuC706x because code
can run in full 32-bit ARM mode and at maximum core speed.
Note that when an exception occurs, the core defaults to ARM
mode.
Remap Operation
When a reset occurs on the ADuC706x, execution starts
automatically in the factory programmed internal configuration
code. This so-called kernel is hidden and cannot be accessed by
user code. If the ADuC706x is in normal mode, it executes the
power-on configuration routine of the kernel and then jumps to
the reset vector, Address 0x00000000, to execute the user’s reset
exception routine. Because the Flash/EE is mirrored at the
bottom of the memory array at reset, the reset routine must
always be written in Flash/EE.
The remap command must be executed from the absolute
Flash/EE address, and not from the mirrored, remapped
segment of memory, as this may be replaced by SRAM. If a
remap operation is executed while operating code from the
mirrored location, prefetch/data aborts can occur or the user
can observe abnormal program operation.
Any kind of reset logically remaps the Flash/EE memory to the
bottom of the memory array.
REMAP Register
Name:
Address:
Default value:
Access:
Function:
REMAP
0xFFFF0220
Updated by the kernel
Read/write access
This 8-bit register allows user code to remap
either RAM or Flash/EE space into the bottom
of the ARM memory space starting at Address
0x00000000.
Rev. PrA | Page 17 of 100
Table 7. REMAP MMR Bit Designations
Bit
7 to 1
0
FLASH/EE CONTROL INTERFACE
Serial and JTAG programming use the Flash/EE control
interface, which includes the eight MMRs outlined in this
section.
FEESTA Register
FEESTA is a read-only register that reflects the status of the
flash control interface as described in Table 7.
Name:
Address:
Default value:
Access:
Table 7. FEESTA MMR Bit Designations
Bit
15:6
5
4
3
2
1
0
FEEMOD Register
FEEMOD sets the operating mode of the flash control interface.
Table 8 shows FEEMOD MMR bit designations.
Name:
Address:
Default value:
Access:
Description
Reserved. These bits are reserved and should be written
as 0 by user code.
Remap Bit.
Set by the user to remap the SRAM to 0x00000000.
Cleared automatically after reset to remap the Flash/EE
memory to 0x00000000.
Description
Reserved.
Reserved.
Reserved.
Flash Interrupt Status Bit. Set automatically when an
interrupt occurs, that is, when a command is complete
and the Flash/EE interrupt enable bit in the FEEMOD
register is set. Cleared when reading FEESTA register.
Flash/EE Controller Busy. Set automatically when the
controller is busy. Cleared automatically when the
controller is not busy.
Command Fail. Set automatically when a command
completes unsuccessfully. Cleared automatically when
reading the FEESTA register.
Command Pass. Set by the MicroConverter® when a
command completes successfully. Cleared
automatically when reading the FEESTA register.
ADuC7060/ADuC7061/ADuC7062
FEESTA
0xFFFF0E00
0x20
Read
FEEMOD
0xFFFF0804
0x0000
Read/write