aduc7062 Analog Devices, Inc., aduc7062 Datasheet - Page 27

• Manufacturer Part Number: aduc7062
• Description: Low-power, Precision Analog Microcontroller, Dual ?-? Adcs, Flash/ee, Arm7tdmi
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
OSCILLATOR, PLL AND POWER CONTROL
Clocking System
Each ADuC7060 integrates a 32.768 kHz ±3% oscillator, a clock
divider, and a PLL. The PLL locks onto a multiple of the internal
oscillator or an external 32.768 kHz crystal to provide a stable 10.24
MHz clock (UCLK) for the system. To allow power saving, the core
can operate at this frequency, or at binary submultiples of it. The
actual core operating frequency, UCLK/2
The default core clock is the PLL clock divided by 8 (CD = 3) or
1.28 MHz.
Table 25.
POWCON[6:3]
1111
1110
1100
1000
0000
Table 26. Typical Current Consumption at 25°C in mA
POWCON[6:3]
1111
1110
1100
1000
0000
*32.768kHz
WATCHDOG
WAKEUP
TIMER
TIMER
±
3%
CORE
Mode
Active
Pause
Nap
Sleep
Stop
Figure 8. Clocking System
OSCILLATOR
Mode
Active
Pause
Nap
Sleep
Stop
INT. 32kHz
OCLK
Core
X
PLL
I
2
CD
C
32.768kHz
10.24MHz
UCLK
CD
Peripherals
X
X
/2
, is refered to as HCLK.
CD
CD = 0
TBD
TBD
TBD
TBD
TBD
HCLK
PERIPHERALS
ANALOG
CD = 1
TBD
TBD
TBD
TBD
TBD
Rev. PrA | Page 27 of 100
PLL
X
X
X
XTAL/T2/T3
X
X
X
CD = 2
TBD
TBD
TBD
TBD
X
TBD
The selection of the clock source is in the PLLCON register. By
default, the part uses the internal oscillator feeding the PLL.
Power Control System
The core clock frequency is changed by writing to the POWCON0
register. This is a key protected register therefore, registers
POWKEY1 and POWKEY2 must be written to immediately before
and after configuring the POWCON0 register. The following is a
simple example showing how to configure the core clock for
10.24 MHz:
POWKEY1 = 0x1;
POWCON0 = 0x78;
POWKEY2 = 0xF4;
A choice of operating modes is available on the ADuC7060. Table
below describes what part is powered on in the different modes and
indicates the power-up time.
Table 26 gives some typical values of the total current consumption
(analog + digital supply currents) in the different modes, depending
on the clock divider bits. The ADC is turned off. Note that these
values also include current consumption of the regulator and other
parts on the test board where these values are measured.
CD = 3
TBD
TBD
TBD
TBD
TBD
ADuC7060/ADuC7061/ADuC7062
IRQ0 to IRQ3
X
X
X
X
X
CD = 4
TBD
TBD
TBD
TBD
TBD
//Set core to max CPU
//speed of 10.24 MHz
CD = 5
TBD
TBD
TBD
TBD
TBD
Start-Up/Power-On Time
CD = 6
TBD
TBD
TBD
TBD
TBD
CD = 7
TBD
TBD
TBD
TBD
TBD