mpc8313e Freescale Semiconductor, Inc, mpc8313e Datasheet - Page 84

• Manufacturer Part Number: mpc8313e
• Description: Mpc8313e Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

System Design Information
Table 64
nominal NV
21.6
The MPC8313E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible
configuration pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when PORESET deasserts, at which time the input receiver is
disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections
to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should
minimize the disruption of signal quality or speed for output pins thus configured.
21.7
The MPC8313E requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins
including I
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
Refer to the PCI 2.2 specification for all pull-ups required for PCI.
21.8
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in
IEEE Std. 1149.1, but is provided on all processors that implement the PowerPC architecture. The device
requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not interfere
with normal chip operation. While it is possible to force the TAP controller to the reset state using only the
TCK and TMS signals, generally systems will assert TRST during power-on reset. Because the JTAG
interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to
PORESET is not practical.
84
Note: Nominal supply voltages. See
Impedance
Differential
R
R
N
P
summarizes the signal impedance targets. The driver impedance are targeted at minimum V
Pull-Up Resistor Requirements
Configuration Pin Muxing
JTAG Configuration Signals
2
C pins, Ethernet Management MDIO pin and EPIC interrupt pins.
DD
, 105°C.
Configuration, Power
Figure
Local Bus, Ethernet,
DUART, Control,
MPC8313E PowerQUICC
Management
42 Target
42 Target
42. Care must be taken to ensure that these pins are maintained at a valid deasserted
NA
Table
Table 64. Impedance Characteristics
1, T
(not including PCI
j
= 105°C.
output clocks)
™
PCI Signals
II Pro Processor Hardware Specifications, Rev. 0
25 Target
25 Target
NA
PCI Output Clocks
PCI_SYNC_OUT)
(including
42 Target
42 Target
NA
DDR DRAM
20 Target
20 Target
NA
Freescale Semiconductor
Symbol
Z
DIFF
Z
Z
0
0
Unit
Ω
Ω
Ω
DD
,