mpc8313e Freescale Semiconductor, Inc, mpc8313e Datasheet - Page 72

• Manufacturer Part Number: mpc8313e
• Description: Mpc8313e Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

Clocking
19.1
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
As described in
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (SYS_CLK_IN or PCI_SYNC_IN) and the internal coherent system bus clock
(csb_clk).
SYS_CLK_IN/PCI_SYNC_IN ratios.
72
CFG_CLKIN_DIV
at reset
System PLL Configuration
Table 59
High
High
High
High
High
Low
Low
Low
1
Section 19,
MPC8313E PowerQUICC
shows the expected frequency values for the CSB frequency for select csb_clk to
SPMF
0010
0011
0100
0101
0110
0010
0011
0100
“Clocking,” The LBCM, DDRCM, and SPMF parameters in the reset
Table 58. System PLL Multiplication Factors
RCWL[SPMF]
0111–1111
0000
0001
0010
0011
0100
0101
0110
Table 59. CSB Frequency Options
Input Clock
csb_clk :
™
Ratio
2 : 1
3 : 1
4 : 1
5 : 1
6 : 1
2 : 1
3 : 1
4 : 1
II Pro Processor Hardware Specifications, Rev. 0
2
System PLL Multiplication
120
144
24
Reserved
Reserved
Reserved
Table 58
Factor
× 2
× 3
× 4
× 5
× 6
csb_clk
Frequency(MHz)
100
125
150
100
25
shows the multiplication factor
Clock
Input
Frequency(MHz)
33.33
100
133
167
100
133
2
Freescale Semiconductor
66.67
133
133