mpc8313e Freescale Semiconductor, Inc, mpc8313e Datasheet - Page 13

• Manufacturer Part Number: mpc8313e
• Description: Mpc8313e Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

4
This section provides the clock input DC and AC electrical characteristics for the MPC8313E.
4.1
Table 6
MPC8313E.
4.2
The primary clock source for the MPC8313E can be one of two inputs, SYS_CLK_IN or PCI_CLK,
depending on whether the device is configured in PCI host or PCI agent mode.
input (SYS_CLK_IN/PCI_CLK) AC timing specifications for the MPC8313E.
Freescale Semiconductor
Input high voltage
Input low voltage
SYS_CLK_IN Input current
PCI_SYNC_IN Input current
PCI_SYNC_IN Input current
SYS_CLK_IN/PCI_CLK frequency
SYS_CLK_IN/PCI_CLK cycle time
SYS_CLK_IN/PCI_CLK rise and fall time
SYS_CLK_IN/PCI_CLK duty cycle
SYS_CLK_IN/PCI_CLK jitter
Notes:
1. Caution: The system, core, security block must not exceed their respective maximum or minimum operating frequencies.
2. Rise and fall times for SYS_CLK_IN/PCI_CLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set
low to allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
Clock Input Timing
provides the clock input (SYS_CLK_IN/PCI_SYNC_IN) DC timing specifications for the
Parameter
DC Electrical Characteristics
AC Electrical Characteristics
Parameter/Condition
MPC8313E PowerQUICC
Table 6. SYS_CLK_IN DC Electrical Characteristics
Table 7. SYS_CLK_IN AC Timing Specifications
NV
0.5 V ≤ V
DD
0 V ≤ V
0 V ≤ V
– 0.5 V ≤ V
Condition
IN
IN
≤ NV
™
t
—
—
IN
KHK
≤ 0.5 V or
II Pro Processor Hardware Specifications, Rev. 0
f
t
≤ NV
SYS_CLK_IN
SYS_CLK_IN
DD
Symbol
/t
t
IN
KH
SYS_CLK_IN
—
– 0.5 V
, t
DD
≤ NV
KL
DD
Min
0.6
25
15
40
—
Symbol
V
V
I
I
I
IN
IN
IN
IH
IL
Typical
0.8
—
—
—
—
–0.3
Min
2.7
—
—
—
Table 7
±150
Max
1.2
66
—
60
NV
provides the clock
DD
Max
±10
±10
±50
0.4
MHz
Unit
ns
ns
ps
%
+ 0.3
Clock Input Timing
Notes
4, 5
Unit
—
μA
μA
μA
1
2
3
V
V
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