mpc8313e Freescale Semiconductor, Inc, mpc8313e Datasheet - Page 15

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mpc8313e

Manufacturer Part Number
mpc8313e
Description
Mpc8313e Powerquicc Ii Pro Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Table 10
Freescale Semiconductor
Time for the device to turn off POR configuration signals with
respect to the assertion of HRESET
Time for the device to turn on POR configuration signals with
respect to the negation of HRESET
Notes:
1. t
2. t
3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
PLL lock times
clock is applied to the SYS_CLK_IN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV.
PCI_SYNC_IN
SYS_CLK_IN
provides the PLL lock times.
is the clock period of the input clock applied to SYS_CLK_IN. It is only valid when the device is in PCI host mode.
is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary
Parameter/Condition
MPC8313E PowerQUICC
Table 9. RESET Initialization Timing Specifications (continued)
Table 10. PLL Lock Times
II Pro Processor Hardware Specifications, Rev. 0
Min
1
Max
100
4
t
PCI_SYNC_IN
Unit
μs
ns
RESET Initialization
Notes
1, 3
3
15

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