mpc8313e Freescale Semiconductor, Inc, mpc8313e Datasheet - Page 20

• Manufacturer Part Number: mpc8313e
• Description: Mpc8313e Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

DDR and DDR2 SDRAM
Figure 4
20
At recommended operating conditions.
MDQS preamble start
MDQS epilogue end
Note:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.
4. Note that t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in
the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same
adjustment value. See the MPC8313E PowerQUICC II Pro Host Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
outputs (A) are setup (S) or output valid time. Also, t
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
symbol conventions described in note 1.
DDKHAS
shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t
symbolizes DDR timing (DD) for the time t
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
Table 19. DDR and DDR2 SDRAM Output AC Timing Specifications (continued)
For the ADDR/CMD setup and hold specifications in
assumed that the clock control register is set to adjust the memory clocks by
1/2 applied cycle.
Parameter
follows the symbol conventions described in note 1. For example, t
MPC8313E PowerQUICC
MCK[n]
MCK[n]
MDQS
MDQS
Figure 4. Timing Diagram for t
™
II Pro Processor Hardware Specifications, Rev. 0
Symbol
t
t
DDKHMP
DDKHME
MCK
DDKLDX
t
t
DDKHMHmax) = 0.6 ns
DDKHMH(min) = –0.6 ns
memory clock reference (K) goes from the high (H) state until
NOTE
1
t
symbolizes DDR timing (DD) for the time t
MCK
–0.5 × t
(first two letters of functional block)(signal)(state) (reference)(state)
for outputs. Output hold time can be read as DDR timing
–0.6
Min
MCK
DDKHMH
– 0.6
Table
DDKHMH
DDKHMH
–0.5 × t
19, it is
can be modified through control
Max
0.6
describes the DDR timing (DD)
MCK
+0.6
Freescale Semiconductor
DDKHMP
MCK
Unit
memory clock
ns
ns
follows the
DDKHMH
Notes
6
6
for
).