mpc8313e Freescale Semiconductor, Inc, mpc8313e Datasheet - Page 46

• Manufacturer Part Number: mpc8313e
• Description: Mpc8313e Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

All values refer to V
I
Figure 28
46
2
Data hold time:
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device (including
hysteresis)
Noise margin at the HIGH level for each connected device (including
hysteresis)
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. The MPC8313E provides a hold time of at least 300 ns for the SDA signal (referred to the V
3. The maximum t
4. C
C
for inputs and t
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
high (H) state or setup time. Also, t
(S) went invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
the undefined region of the falling edge of SCL.
B
= capacitance of one bus line in pF.
provides the AC test load for the I
IH
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
(min) and V
MPC8313E PowerQUICC
has only to be met if the device does not stretch the LOW period (t
Output
IL
Parameter
(max) levels (see
Table 43. I
I2SXKL
I2C
clock reference (K) going to the low (L) state or hold time. Also, t
symbolizes I
2
CBUS compatible masters
C AC Electrical Specifications (continued)
Figure 28. I
Table
Z
™
0
II Pro Processor Hardware Specifications, Rev. 0
= 50 Ω
42).
2
C.
I
2
2
C timing (I2) for the time that the data with respect to the start condition
C bus devices
2
C AC Test Load
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
Symbol
t
t
t
I2PVKH
I2KHDX
I2DXKL
t
t
V
R
V
I2CR
I2CF
NH
NL
L
= 50 Ω
1
20 + 0.1 C
20 + 0.1 C
0.1 × NV
0.2 × NV
I2C
Min
NV
0
0.6
1.3
—
I2CL
IHmin
2
DD
clock reference (K) going to the
) of the SCL signal.
DD
DD
I2DVKH
/2
B
B
of the SCL signal) to bridge
4
4
Freescale Semiconductor
I2PVKH
symbolizes I
0.9
Max
300
300
—
—
—
—
—
3
symbolizes I
2
I2C
C timing
Unit
μs
ns
ns
μs
μs
clock
V
V
2
C