mpc8313e Freescale Semiconductor, Inc, mpc8313e Datasheet - Page 71

• Manufacturer Part Number: mpc8313e
• Description: Mpc8313e Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

Table 57
operating conditions (see
Freescale Semiconductor
e300 core frequency ( core_clk )
Coherent system bus frequency
( csb_clk )
DDR1/2 memory bus frequency
(MCK)
Local bus frequency
(LCLK n )
PCI input frequency (SYS_CLK_IN or PCI_CLK)
2. The DDR data rate is 2x the DDR memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lbc_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
Notes:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting
frequencies. The value of SCCR[ENCCM] and SCCR[USBDRCM] must be programmed such that the maximum internal
operating frequency of the Security core and USB modules will not exceed their respective value listed in this table.
the csb_clk frequency (depending on RCWL[LBCM]).
csb_clk , MCK, LCLK[0:1], and core_clk frequencies do not exceed their respective maximum or minimum operating
2
3
provides the operating frequencies for the MPC8313E TEPBGA II under recommended
TSEC1
TSEC2
Security Core, I2C, SAP, TPR
USB DR
PCI and DMA complex
MPC8313E PowerQUICC
Table
Characteristic
Unit
Table 57. Operating Frequencies for TEPBGA I I
2).
Table 56. Configurable Clock Units
1
™
II Pro Processor Hardware Specifications, Rev. 0
Frequency
csb_clk
csb_clk
csb_clk
csb_clk
csb_clk
Default
Off,
Off,
Off,
Off, csb_clk, csb_clk/2,
Off,
csb_clk
csb_clk
csb_clk
csb_clk
Max Operating Frequency
,
,
, csb_clk/2,
Options
csb_clk
csb_clk
33–66
24–66
333
167
167
/2,
/2,
csb_clk
csb_clk
csb_clk
csb_clk
/3
/3
/3
/3
MHz
Unit
MHz
MHz
MHz
MHz
Clocking
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