mpc8313e Freescale Semiconductor, Inc, mpc8313e Datasheet - Page 73

• Manufacturer Part Number: mpc8313e
• Description: Mpc8313e Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

19.2
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk).
not listed in
Freescale Semiconductor
0–1
1
2
nn
11
00
01
10
00
01
10
00
01
10
00
01
CFG_CLKIN_DIV
RCWL[COREPLL]
CFG_CLKIN_DIV select the ratio between SYS_CLK_IN and PCI_SYNC_OUT.
SYS_CLK_IN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
at reset
Core PLL Configuration
Low
Low
nnnn
0000
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
2–5
Table 60
Core VCO frequency = Core frequency × VCO divider
VCO divider has to be set properly so that the core VCO frequency is in the
range of 400–800 MHz.
1
MPC8313E PowerQUICC
should be considered as reserved.
6
0
n
0
0
0
1
1
1
0
0
0
1
1
Table 60
SPMF
0101
0110
Table 59. CSB Frequency Options (continued)
(PLL off, csb_clk clocks core directly)
shows the encodings for RCWL[COREPLL]. COREPLL values that are
Table 60. e300 Core PLL Configuration
core_clk : csb_clk Ratio
Input Clock
PLL bypassed
csb_clk :
™
Ratio
5 : 1
6 : 1
II Pro Processor Hardware Specifications, Rev. 0
1.5:1
1.5:1
1.5:1
2.5:1
2.5:1
n/a
1:1
1:1
1:1
2:1
2:1
2:1
2
NOTE
120
144
24
csb_clk
Frequency(MHz)
(PLL off, csb_clk clocks core directly)
125
150
25
Clock
Input
Frequency(MHz)
VCO divider
PLL bypassed
33.33
167
2
n/a
2
4
8
2
4
8
2
4
8
2
4
1
66.67
Clocking
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