mpc8536e Freescale Semiconductor, Inc, mpc8536e Datasheet - Page 94

• Manufacturer Part Number: mpc8536e
• Description: Mpc8536e Powerquicctm Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

High-Speed Serial Interfaces
2.20.2.2 DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the MPC8536E SerDes reference clock inputs is different depending on the signaling mode used
to connect the clock driver chip and SerDes reference clock inputs as described below.
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SD n _REF_CLK
SD n _REF_CLK
Differential Mode
— The input amplitude of the differential clock must be between 400mV and 1600mV differential peak-peak (or
— For external DC-coupled connection, as described in section 2.20.2.1, the maximum average current
— For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since
Single-ended Mode
— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude (single-ended swing) must be
— The SDn_REF_CLK input average voltage must be between 200 and 400 mV.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or AC-coupled
Figure 59. Differential Reference Clock Input DC Requirements (External DC-Coupled)
between 200mV and 800mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing less than 800mV and greater than 200mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
requirements sets the requirement for average voltage (common mode voltage) to be between 100 mV and 400
mV.
the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver
operate in different command mode voltages. The SerDes reference clock receiver in this connection scheme has
its common mode voltage set to SnGND. Each signal wire of the differential inputs is allowed to swing below and
above the command mode voltage (SnGND).
AC-coupled connection scheme.
between 400mV and 800mV peak-peak (from Vmin to Vmax) with SDn_REF_CLK either left unconnected or
tied to ground.
reference clock input requirement for single-ended signaling mode.
externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused
phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use.
Figure 59
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
200 mV < Input Amplitude or Differential Peak < 800 mV
shows the SerDes reference clock input requirement for DC-coupled connection scheme.
Figure 60
shows the SerDes reference clock input requirement for
Figure 61
100 mV < Vcm < 400 mV
Freescale Semiconductor
shows the SerDes
Vmax < 800 mV
Vmin > 0 V