mpc8536e Freescale Semiconductor, Inc, mpc8536e Datasheet - Page 20

• Manufacturer Part Number: mpc8536e
• Description: Mpc8536e Powerquicctm Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Pin Map
20
Notes:
1. All multiplexed signals may be listed only once and may not re-occur.
2. Recommend a weak pull-up resistor (2–10 KΩ) be placed on this pin to OV
3. This pin must always be pulled-high.
4. This pin is an open drain signal.
5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
6. Treat these pins as no connects (NC) unless using debug address functionality.
7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down
8. The value of LALE, LGPL2 and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ
9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
10. For proper state of these signals during reset, these pins can be left without any pulldowns, thus relying on the internal
11. This output is actively driven during reset rather than being three-stated during reset.
12. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13. These pins are connected to the V
15. These pins have other manufacturing or debug test functions. It is recommended to add both pull-up resistor pads to OVDD
16. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe
17. This pin is only an output in FIFO mode when used as Rx Flow Control.
18. Do not connect.
19.These must be pulled up (100 Ω- 1 kΩ) to OVDD.
20. Independent supplies derived from board VDD.
21. Recommend a pull-up resistor (1 KΩ) be placed on this pin to OV
22. The following pins must NOT be pulled down during power-on reset: MDVAL, UART_SOUT[0:1], EC_MDC,
23. This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is
24. General-Purpose POR configuration of user system.
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. However, if
the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net
at reset, then a pullup or active driver is needed.
resistors. See
pull-up or pull-down resistors. See the
because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.
pullup to get the values to the require 2'b11.However, if there is any device on the net which might pull down the value of the
net at reset, then a pullup is needed.
improve tracking and regulation.
and pull-down resistor pads to GND on board to support future debug testing when needed.
state during reset.
TSEC1_TXD[3], TSEC3_TXD[7], HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP.
actively driven.
Signal
Section 22.2, “CCB/SYSCLK PLL
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Table 1. MPC8536E Pinout Listing (continued)
DD_CORE
Signal Name
Section 22.3, “e500 Core PLL
/V
DD_PLAT
Ratio.”
/GND planes internally and may be used by the core power supply to
Package Pin Number
DD
.
Ratio.”
DD
.
Pin Type
Freescale Semiconductor
Supply
Power
Notes