mpc8536e Freescale Semiconductor, Inc, mpc8536e Datasheet - Page 24

• Manufacturer Part Number: mpc8536e
• Description: Mpc8536e Powerquicctm Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Overall DC Electrical Characteristics
Figure 2
The core voltage must always be provided at nominal 1.0 Vor 1.1 V (See
to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in
Table
are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR2 and DDR3 SDRAM interface
uses differential receivers referenced by the externally supplied MV
for the SSTL_1.8 electrical signaling standard for DDR2 or 1.5-V electrical signaling for DDR3. The DDR DQS receivers
cannot be operated in single-ended fashion. The complement signal must be properly driven and cannot be grounded.
24
2. The input voltage threshold scales with respect to the associated I/O supply voltage. OV
shows the undershoot and overshoot voltages at the interfaces of the MPC8536E.
V
IH
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
V
Note:
1. t
2. With the PCI overshoot allowed (as specified above), the device
IL
Figure 7. Overshoot/Undershoot Voltage for GV
B/G/L/OV
For I
For DDR, t
For eTSEC, t
For eLBC, t
For PCI, t
does not fully comply with the maximum AC ratings and device protection
guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3).
CLOCK
B/G/L/OV
2
C and JTAG, t
GND – 0.3 V
GND – 0.7 V
B/G/L/OV
refers to the clock period associated with the respective interface:
DD
CLOCK
DD
CLOCK
CLOCK
+ 20%
CLOCK
+ 5%
GND
DD
references PCI1_CLK or SYSCLK.
references MCLK.
references LCLK.
CLOCK
references EC_GTX_CLK125.
references SYSCLK.
Not to Exceed 10%
REF
of t
Table 2
n signal (nominally set to GV
CLOCK
for actual recommended core voltage). Voltage
1
DD
/OV
DD
/LV
DD
DD
and LV
Freescale Semiconductor
DD
/2) as is appropriate
DD
based receivers