mpc8536e Freescale Semiconductor, Inc, mpc8536e Datasheet - Page 87

• Manufacturer Part Number: mpc8536e
• Description: Mpc8536e Powerquicctm Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

All values refer to V
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device
(including hysteresis)
Noise margin at the HIGH level for each connected device
(including hysteresis)
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. As a transmitter, the MPC8536E provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL
3. The maximum t
4. C
Figure 51
Freescale Semiconductor
for inputs and t
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
high (H) state or setup time. Also, t
(S) went invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.
When the MPC8536E acts as the I
load on SCL and SDA are balanced, the MPC8536E would not cause unintended generation of Start or Stop condition.
Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time
is required for the MPC8536E as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register
to ensure both the desired I
SCL clock frequency is 400 KHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default
setting of 0x10 (decimal 16):
For details of the I
the I
B
= capacitance of one bus line in pF.
I
FDR Bit Setting
Actual FDR Divider Selected
Actual I
2
2
C Source Clock Frequency is half of the CCB clock frequency for the MPC8536E.
C Source Clock Frequency
provides the AC test load for the I
2
C SCL Frequency Generated
IH
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
(min) and V
2
C frequency calculation, refer to Determining the I
has only to be met if the device does not stretch the LOW period (t
Parameter
Output
IL
2
C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I
(max) levels (see
Table 64. I
I2SXKL
2
I2C
C bus master while transmitting, the MPC8536E drives both SCL and SDA. As long as the
clock reference (K) going to the low (L) state or hold time. Also, t
symbolizes I
2
2
C AC Electrical Specifications (continued)
C.
Figure 51. I
Table
371 KHz
333 MHz
0x2A
896
Z
0
= 50 Ω
63).
2
C timing (I2) for the time that the data with respect to the start condition
266 MHz
0x05
704
378 KHz
2
C AC Test Load
Symbol
t
I2KHDX
V
V
NH
2
NL
for outputs. For example, t
C Frequency Divider Ratio for SCL (AN2919). Note that
200 MHz
0x26
512
390 KHz
(first two letters of functional block)(signal)(state) (reference)(state)
1
R
L
0.1 × OV
0.2 × OV
= 50 Ω
Min
1.3
133 MHz
0x00
384
346 KHz
DD
DD
I2C
OV
I2CL
DD
clock reference (K) going to the
) of the SCL signal.
Max
I2DVKH
/2
—
—
—
symbolizes I
I2PVKH
Unit
μs
V
V
symbolizes I
2
C timing
I2C
Notes
—
—
—
clock
2
2
I
2
87
C
C
C