mpc8536e Freescale Semiconductor, Inc, mpc8536e Datasheet - Page 61
mpc8536e
Manufacturer Part Number
mpc8536e
Description
Mpc8536e Powerquicctm Iii Integrated Processor Hardware Specifications
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC8536E.pdf
(128 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
mpc8536eAVTAKG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
mpc8536eAVTAKGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
mpc8536eAVTANG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
mpc8536eAVTANGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
mpc8536eAVTAOG
Manufacturer:
FREESCAL
Quantity:
156
Part Number:
mpc8536eAVTAQGA
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
mpc8536eAVTATGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
mpc8536eBVTANG
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
mpc8536eBVTATHA
Manufacturer:
FREESCAL
Quantity:
159
Company:
Part Number:
mpc8536eBVTAULA
Manufacturer:
FREESCAL
Quantity:
850
Company:
Part Number:
mpc8536eBVTAVL
Manufacturer:
FREESCAL
Quantity:
160
The IEEE 1588 AC timing specifications are in
2.10
The electrical characteristics specified here apply to MII management interface signals EC_MDIO (management data
input/output) and EC_MDC (management data clock). The electrical characteristics for GMII, SGMII, RGMII, RMII, TBI and
RTBI are specified in
Freescale Semiconductor
At recommended operating conditions with L/TV
TSEC_1588_CLK clock period
TSEC_1588_CLK duty cycle
TSEC_1588_CLK peak-to-peak jitter
Rise time eTSEC_1588_CLK (20%–80%)
Fall time eTSEC_1588_CLK (80%–20%)
TSEC_1588_CLK_OUT clock period
TSEC_1588_CLK_OUT duty cycle
TSEC_1588_PULSE_OUT
TSEC_1588_TRIG_IN pulse width
Note:
1. When TMR_CTRL[CKSEL]=00, the external TSEC_1588_CLK input is selected as the 1588 timer reference clock source,
2. It need to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8536E
with the timing defined in the Table above. The maximum value of t
maximum clock cycle period of the equivalent interface speed that the eTSEC1 port is running
When eTSEC1 is configured to operate in the parallel mode, the T
TSEC1_TX_CLK. When eTSEC1 operates in SGMII mode, the maximum value of t
recovered clock from SGMII SerDes. For example, for 10/100/1000 Mbps modes, the maximum value of t
2800, 280, and 56 ns respectively.
See the MPC8536E PowerQUICC™ III Integrated Communications Processor Reference Manual for a description of
TMR_CTRL registers.
PowerQUICC™ III Integrated Processor Reference Manual for a description of TMR_CTRL registers.
Parameter/Condition
Ethernet Management Interface Electrical Characteristics
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
Section 2.9, “Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management”
Table 43. eTSEC IEEE 1588 AC Timing Specifications
DD
of 3.3 V ± 5%.
/t
t
t
t
t
t
T1588CLKOUT
T1588CLKOTH
t
T1588CLKINR
T1588CLKOUT
T1588CLKINJ
T1588CLKINF
Table
t
T1588TRIGH
/t
t
T1588CLKH
t
Symbol
T1588CLK
T1588CLK
T1588OV
43.
2*t
Ethernet Management Interface Electrical Characteristics
2*t
T1588CLK_MAX
T1588CLK
Min
3.8
1.0
1.0
0.5
TX_CLK
40
30
—
T1588CLK
is the maximum clock period of the
is defined in terms of T
Typ
50
50
—
—
—
—
—
—
—
T1588CLK
T
TX_CLK
is defined in terms of the
Max
250
2.0
2.0
3.0
60
70
—
—
.
*7
TX_CLK
T1588CLK
Unit
, which is the
ns
ps
ns
ns
ns
ns
ns
%
%
will be
Note
—
—
—
—
—
—
—
1
2
61