mpc8536e Freescale Semiconductor, Inc, mpc8536e Datasheet - Page 116

• Manufacturer Part Number: mpc8536e
• Description: Mpc8536e Powerquicctm Iii Integrated Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Pin States in Deep Sleep State
3.3
In all low power mode by default, all input and output pads remain driven as per normal functional operation. The inputs remain
enabled.
The exception is that in Deep Sleep mode, GCR[DEEPSLEEP_Z] can be used to tristate a subset of output pads, and disable
the receivers of input pads as defined in
Manual for details.
3.4
Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high
frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching
other components in the MPC8536E system, and the device itself requires a clean, tightly regulated source of power. Therefore,
it is recommended that the system designer place at least one decoupling capacitor at each V
and LV
GV
must be placed directly under the device using a standard escape pattern as much as possible. If some caps are to be placed
surrounding the part it should be routed with short and large trace to minimize the inductance.
These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to
minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the V
BV
have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected
to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON). However, customers should work directly with their power regulator vendor for best values types
and quantity of bulk capacitors.
3.5
he SerDes1 and SerDes2 blocks require a clean, tightly regulated source of power (SnV
transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to
power and ground should be done with multiple vias to further reduce inductance.
3.6
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active
low inputs should be tied to V
connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all
external V
116
DD
DD
•
•
•
, and LV
, OV
DD
First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls
of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and
ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the
device as close to the supply and ground connections as possible.
Second, there should be a 1-µF ceramic chip capacitor from each SerDes supply (SnV
ground plane on each side of the device. This should be done for all SerDes supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-µF, low equivalent series resistance
(ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all
SerDes supplies.
DD,
pin of the device. These decoupling capacitors should receive their power from separate V
DD
Pin States in Deep Sleep State
Decoupling Recommendations
SerDes Block Power Supply Decoupling Recommendations
Connection Recommendations
TV
, GV
DD
DD
, and GND power planes in the PCB, utilizing short low impedance traces to minimize inductance. Capacitors
DD
MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2
, BV
, and LV
DD
, OV
DD
DD,
DD
planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should
TV
, GV
DD
, BV
DD
Table
, and LV
DD
1. See the MPC8536E PowerQUICC™ III Integrated Processor Reference
, OV
DD
DD
, GV
and GND pins of the device.
DD
, and LV
DD
as required. All unused active high inputs should be
DD
and XnV
DD
, TV
DD
and XnV
DD
DD
DD,
Freescale Semiconductor
, BV
) to ensure low jitter on
TV
DD
DD
DD
, OV
, BV
) to the board
DD
DD
DD
, GV
, OV
, TV
DD
DD
DD
,
,
,