dac1208d650 NXP Semiconductors, dac1208d650 Datasheet - Page 95

dac1208d650

Manufacturer Part Number

dac1208d650

Description

Dac1208d650 Dual 12-bit Dac; Up To 650 Msps; 2?, 4? Or 8? Interpolating With Jesd204a Interface

Manufacturer

NXP Semiconductors

Datasheet

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Table 59. Page 2 register allocation map . . . . . . . . . . . .51

Table 60. MAINCONTROL register (address 00h)

Table 61. JCLK_CNTRL register (address 03h)

Table 62. RST_EXT_FCLK register (address 04h)

Table 63. RST_EXT_DCLK register (address 05h)

Table 64. DCSMU_PREDIVCNT register (address 06h)

Table 65. PLL_CHARGETIME register (address 07h)

Table 66. PLL_RUN_IN_TIME register (address 08h)

Table 67. CA_RUN_IN_TIME register (address 09h)

Table 68. SET_VCM_VOLTAGE register (address 16h)

Table 69. SET_SYNC register (address 17h)

Table 70. TYPE_ID register (address 1Bh)

Table 71. DAC_VERSION register (address 1Ch)

Table 72. DIG_VERSION register (address 1Dh)

Table 73. JRX_ANA_VERSION register (address 1Eh)

Table 74. PAGE_ADDRESS register (address 1Fh)

Table 75. Lane common-mode voltage adjustment . . . . .55

Table 76. SYNC common-mode voltage adjustment . . . .55

Table 77. SYNC swing voltage adjustment . . . . . . . . . . .55

Table 78. Page 4 register allocation map . . . . . . . . . . . .56

Table 79. SR_DLP_0 register (address 00h)

Table 80. SR_DLP_1 register (address 01h)

Table 81. FORCE_LOCK register (address 02h)

Table 82. MAN_LOCK_LN_1_0 register (address 03h)

Table 83. MAN_LOCK_2_0 register (address 04h)

Table 84. CA_CNTRL register (address 05h)

Table 85. SCR_CNTRL register (address 06h)

Table 86. ILA_CNTRL register (address 07h)

DAC1208D650

Product data sheet

bit description . . . . . . . . . . . . . . . . . . . . . . . . .50

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bit description . . . . . . . . . . . . . . . . . . . . . . . . .60

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 14 December 2010

2×, 4× or 8× interpolating DAC with JESD204A interface

Table 87. FORCE_ALIGN register (address 08h)

Table 88. MAN_ALIGN_LN_0_1 register (address 09h)

Table 89. MAN_ALIGN_LN_2_3 register (address 0Ah)

Table 90. FA_ERR_HANDLING register (address 0Bh)

Table 91. SYNCOUT_MODE register (address 0Ch)

Table 92. LANE_POLARITY register (address 0Dh)

Table 93. LANE_SELECT register (address 0Eh)

Table 94. SOFT_RESET_SCRAMBLER register

Table 95. INIT_SCR_S15T8_LN0 register

Table 96. INIT_SCR_S7T1_LN0 (address 12h)

Table 97. INIT_SCR_S15T8_LN1 register (address 13h)

Table 98. INIT_SCR_S7T1_LN1 register (address 14h)

Table 99. INIT_SCR_S15T8_LN2 register (address 15h)

Table 100. INIT_SCR_S7T1_LN2 register (address 16h)

Table 101. INIT_SCR_S15T8_LN3 register (address 17h)

Table 102. INIT_SCR_S7T1_LN3 register (address 18h)

Table 103. INIT_ILA_BUFPTR_LN01 register (address 19h)

Table 104. INIT_ILA_BUFPTR_LN23 register (address 1Ah)

Table 105. ERROR_HANDLING register (address 1Bh)

Table 106. REINIT_CNTRL register (address 1Ch)

Table 107. PAGE_ADDRESS register (address 1Fh)

Table 108. Page 5 register allocation map . . . . . . . . . . . . 68

Table 109. ILA_MON_1_0 register (address 00h)

Table 110. ILA_MON_3_2 register (address 01h)

Table 111. ILA_BUF_ERR register (address 02h)

Table 112. CA_MON register (address 03h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64

(address 10h) bit description . . . . . . . . . . . . . . 64

(address 11h) bit description . . . . . . . . . . . . . . 64

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 66

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 67

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 70

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