dac1208d650 NXP Semiconductors, dac1208d650 Datasheet - Page 42

• Manufacturer Part Number: dac1208d650
• Description: Dac1208d650 Dual 12-bit Dac; Up To 650 Msps; 2?, 4? Or 8? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 24.
Table 25.
Table 26.
Table 27.
Default settings are shown highlighted.
Table 28.
Table 29.
DAC1208D650
Product data sheet
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7
6
5 to 0
Bit
7 to 6
5 to 0
Bit
7 to 6
5 to 0
Symbol
FREQ_NCO[31:24]
Symbol
PH_NCO[7:0]
Symbol
PH_NCO[15:8]
Symbol
DAC_A_PD
DAC_A_SLEEP
DAC_A_OFFSET[5:0]
Symbol
DAC_A_GAIN_COARSE[1:0]
DAC_A_GAIN_FINE[5:0]
Symbol
DAC_A_GAIN_COARSE[3:2]
DAC_A_OFFSET[11:6]
FREQNCO_MSB register (address 06h) bit description
PHINCO_LSB register (address 07h) bit description
PHINCO_MSB register (address 08h) bit description
DAC_A_CFG_1 register (address 09h) bit description
DAC_A_CFG_2 register (address 0Ah) bit description
DAC_A_CFG_3 register (address 0Bh) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 December 2010
Access
R/W
Access
R/W
Access
R/W
Access
R/W
R/W
R/W
Access
R/W
R/W
Access
R/W
R/W
2×, 4× or 8× interpolating DAC with JESD204A interface
Value
26h
Value
00h
Value
00h
Value
0
1
0
1
00h
Value
1h
00h
Value
3h
00h
Description
most significant 8 bits for the NCO frequency setting
Description
lower 8 bits for the NCO phase setting
Description
most significant 8 bits for the NCO phase setting
Description
DAC A power
DAC A Sleep mode
lower 6 bits for the DAC A offset
Description
least significant 2 bits for the DAC A gain setting for
coarse adjustment
the 6 bits for the DAC A gain setting for fine
adjustment
Description
most significant 2 bits for the DAC A gain setting for
coarse adjustment
most significant 6 bits for the DAC A offset
on
off
disabled
enabled
DAC1208D650
© NXP B.V. 2010. All rights reserved.
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