dac1208d650 NXP Semiconductors, dac1208d650 Datasheet - Page 62

• Manufacturer Part Number: dac1208d650
• Description: Dac1208d650 Dual 12-bit Dac; Up To 650 Msps; 2?, 4? Or 8? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 89.
Table 90.
Default settings are shown highlighted.
DAC1208D650
Product data sheet
Bit
7 to 4
3 to 0
Bit
7 to 6
5 to 4
3 to 2
1 to 0
Symbol
MAN_ALIGN_LN3[3:0]
MAN_ALIGN_LN2[3:0]
Symbol
SEL_KOUT_ UNEXP_LN23[1:0]
SEL_KOUT_ UNEXP_LN10[1:0]
SEL_NIT_ERR_ LN23[1:0]
SEL_NIT_ERR_ LN10[1:0]
MAN_ALIGN_LN_2_3 register (address 0Ah) bit description
FA_ERR_HANDLING register (address 0Bh) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 December 2010
Access
R/W
R/W
Access
R/W
R/W
R/W
R/W
2×, 4× or 8× interpolating DAC with JESD204A interface
Value
0h
0h
Value
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Description
indicates alignment data-delay for lane 3 [1..15]
indicates alignment data-delay for lane 2 [1..15]
Description
lane 2/lane 3 unexpected /K/ error handling
lane 0/lane 1 unexpected /K/ error handling
lane 2/lane 3 nit-error handling
lane 0/lane 1 nit-error handling
unexpected /K/ in lane 2 or lane 3
error_handling
unexpected /K/ in lane 2 and lane 3 error_handling
unexpected /K/ in lane 2 error_handling
unexpected /K/ in lane 3 error_handling
unexpected /K/ in lane 0 or lane 1
error_handling
unexpected /K/ in lane 0 and lane 1 error_handling
unexpected /K/ in lane 0 error_handling
unexpected /K/ in lane 1 error_handling
nit-errors in lane 2 or lane 3 error_handling
not-in-table errors lane 2 and lane 3
error_handling
not-in-table errors in lane 2 error_handling
not-in-table errors in lane 3 error_handling
nit-errors in lane 0 or lane 1 error_handling
not-in-table errors lane 0 and lane 1
error_handling
not-in-table errors in lane 0 error_handling
not-in-table errors in lane 1 error_handling
DAC1208D650
© NXP B.V. 2010. All rights reserved.
62 of 98