dac1208d650 NXP Semiconductors, dac1208d650 Datasheet - Page 30

• Manufacturer Part Number: dac1208d650
• Description: Dac1208d650 Dual 12-bit Dac; Up To 650 Msps; 2?, 4? Or 8? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1208D650
Product data sheet
10.10 Digital offset correction
Table 13.
Default settings are shown highlighted.
The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see
“DAC_A_CFG_2 register (address 0Ah) bit
(register 0Dh; see
define the fine variation of the full-scale current (see
Table 14.
Default settings are shown highlighted.
The coding of the fine gain adjustment is two’s complement.
When the DAC1208D650 analog output is DC connected to the next stage, the digital
offset correction can be used to adjust the common-mode level at the output of the DAC.
It adds an offset at the end of the digital part, just before the DAC.
The settings applied to DAC_A_OFFSET[11:0] (register 09h; see
“DAC_A_CFG_1 register (address 09h) bit description”
“DAC_A_CFG_3 register (address 0Bh) bit
DAC_GAIN_COARSE[3:0]
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DAC_GAIN_FINE[5:0]
Decimal
−32
...
0
...
31
I
I
O(fs)
O(fs)
coarse adjustment
fine adjustment
All information provided in this document is subject to legal disclaimers.
Table 31 “DAC_B_CFG_2 register (address 0Dh) bit
Rev. 2 — 14 December 2010
2×, 4× or 8× interpolating DAC with JESD204A interface
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Two’s complement
10 0000
...
00 0000
...
01 1111
description”) and to DAC_B_GAIN_FINE[5:0]
description”) and to “DAC_B_OFFSET[11:0]”
Table
and register 0Bh; see
14).
DAC1208D650
I
1.6
3.0
4.4
5.8
7.2
8.6
10.0
11.4
12.8
14.2
15.6
17.0
18.5
20.0
21.0
22.0
Delta I
−10 %
...
0
...
+10 %
O(fs)
(mA)
Table 27
O(fs)
Table 28
© NXP B.V. 2010. All rights reserved.
description”)
Table 29
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