dac1208d650 NXP Semiconductors, dac1208d650 Datasheet - Page 31

• Manufacturer Part Number: dac1208d650
• Description: Dac1208d650 Dual 12-bit Dac; Up To 650 Msps; 2?, 4? Or 8? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1208D650
Product data sheet
10.11 Analog output
(register 0Ch; see
register 0Eh; see
the range of variation of the digital offset (see
Table 15.
Default settings are shown highlighted.
The DAC1208D650 has two output channels each of which produces two complementary
current outputs. These allow the even-order harmonics and noise to be reduced. The pins
are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected via a
load resistor R
The equivalent analog output circuit of one DAC is shown in
consists of a parallel combination of NMOS current sources and their associated switches
for each segment.
The cascode source configuration increases the output impedance of the source, thus
improving the dynamic performance of the DAC by introducing less distortion.
The device can provide an output level (V
the following stages and the targeted performances.
DAC_OFFSET[11:0]
Decimal
−2048
−2047
...
−1
0
+1
...
2046
2047
Fig 18. Equivalent analog output circuit (one DAC)
Digital offset adjustment
L
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to the 3.3 V analog power supply (V
Table 32 “DAC_B_CFG_3 register (address 0Eh) bit
Table 30 “DAC_B_CFG_1 register (address 0Ch) bit description”
Rev. 2 — 14 December 2010
AGND
2×, 4× or 8× interpolating DAC with JESD204A interface
Two’s complement
1000 0000 0000
1000 0000 0001
...
1111 1111 1111
0000 0000 0000
0000 0000 0001
...
0111 1111 1110
0111 1111 1111
AGND
o(p-p)
Table
) of up to 2 V, depending on the application,
IOUTAP/IOUTBP
IOUTAN/IOUTBN
15).
DDA(3V3)
DAC1208D650
).
Offset applied
−4096
−4094
...
−2
0
+2
...
+4092
+4094
Figure
V
DDA(3V3)
R L
001aah019
18. This circuit
R L
description”) define
© NXP B.V. 2010. All rights reserved.
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and