dac1208d650 NXP Semiconductors, dac1208d650 Datasheet - Page 53

• Manufacturer Part Number: dac1208d650
• Description: Dac1208d650 Dual 12-bit Dac; Up To 650 Msps; 2?, 4? Or 8? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 62.
Default settings are shown highlighted.
Table 63.
Default settings are shown highlighted.
Table 64.
Default settings are shown highlighted.
Table 65.
Default settings are shown highlighted.
Table 66.
Default settings are shown highlighted.
Table 67.
Default settings are shown highlighted.
Table 68.
Default settings are shown highlighted.
Table 69.
Default settings are shown highlighted.
DAC1208D650
Product data sheet
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
3 to 0
Bit
6 to 4
2 to 0
Symbol
RST_EXT_FCLK_TIME[7:0]
Symbol
RST_EXT_DCLK_TIME[7:0]
Symbol
DCSMU_PREDIVIDER[7:0]
Symbol
PLL_CHARGE_TIME[7:0]
Symbol
PLL_RUNIN_TIME[7:0]
Symbol
CA_RUNIN_TIME[7:0]
Symbol
SET_VCM[3:0]
Symbol
SET_SYNC_VCOM[2:0]
SET_SYNC_LEVEL[2:0]
RST_EXT_FCLK register (address 04h) bit description
RST_EXT_DCLK register (address 05h) bit description
DCSMU_PREDIVCNT register (address 06h) bit description
PLL_CHARGETIME register (address 07h) bit description
PLL_RUN_IN_TIME register (address 08h) bit description
CA_RUN_IN_TIME register (address 09h) bit description
SET_VCM_VOLTAGE register (address 16h) bit description
SET_SYNC register (address 17h) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 December 2010
Access
R/W
Access
R/W
Access
R/W
Access
R/W
Access
R/W
Access
R/W
Access
R/W
Access
R/W
R/W
2×, 4× or 8× interpolating DAC with JESD204A interface
Value
Value
20h
Value
1Eh
Value
32h
Value
32h
Value
04h
Value
02h
Value
4h
3h
3Fh
Description
Description
specifies extension time reset_dclk (in dclk-periods)
Description
value used by dcsmu predivider (at f
Description
PLL charge time
(at f
Description
Description
clock alignment run in time
(at f
Description
Description
set synchronization transmitter common-mode level
(see
(see
specifies extension time reset_fclk in f
PLL run in time (at f
set lane common-mode voltage (see
set synchronization transmitter output level swing
clk
clk
Table
Table
/DCSMU_PREDIVIDER[7:0])
/DCSMU_PREDIVIDER[7:0])
76)
77)
DAC1208D650
clk
/DCSMU_PREDIVIDER[7:0])
© NXP B.V. 2010. All rights reserved.
clk
Table
clk
)
periods
75)
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