dac1208d650 NXP Semiconductors, dac1208d650 Datasheet - Page 86

• Manufacturer Part Number: dac1208d650
• Description: Dac1208d650 Dual 12-bit Dac; Up To 650 Msps; 2?, 4? Or 8? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 182. LN2_CFG_8 register (address 08h) bit description
Default settings are shown highlighted.
Table 183. LN2_CFG_9 register (address 09h) bit description
Default settings are shown highlighted.
Table 184. LN2_CFG_10 register (address 0Ah) bit description
Default settings are shown highlighted.
Table 185. LN2_CFG_11 register (address 0Bh) bit description
Default settings are shown highlighted.
Table 186. LN2_CFG_12 register (address 0Ch) bit description
Default settings are shown highlighted.
Table 187. LN2_CFG_13 register (address 0Dh) bit description
Default settings are shown highlighted.
Table 188. LN3_CFG_0 register (address 10h) bit description
Default settings are shown highlighted.
Table 189. LN3_CFG_1 register (address 11h) bit description
Default settings are shown highlighted.
Table 190. LN3_CFG_2 register (address 12h) bit description
Default settings are shown highlighted.
DAC1208D650
Product data sheet
Bit
4 to 0
Bit
4 to 0
Bit
7
4 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
3 to 0
Bit
4 to 0
Symbol
LN2_N'[4:0]
Symbol
LN2_S[4:0]
Symbol
LN2_HD
LN2_CF[4:0]
Symbol
LN2_RES1[7:0]
Symbol
LN2_RES2[7:0]
Symbol
LN2_FCHK[7:0]
Symbol
LN3_DID[7:0]
Symbol
LN3_BID[3:0]
Symbol
LN3_LID[4:0]
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 December 2010
Access
R
Access
R
Access
R
R
Access
R
Access
R
Access
R
Access
R
Access
R
Access
R
2×, 4× or 8× interpolating DAC with JESD204A interface
Value
-
Value
-
Value
-
-
Value
-
Value
-
Value
Value
-
Value
-
Value
-
-
Description
number of bits per sample minus 1
Description
number of samples per converter per frame cycle
minus 1
Description
high density
number of control words per frame cycle
Description
lane 2 reserved field
Description
lane 2 reserved field
Description
Description
lane 3 device ID
Description
lane 3 bank ID
Description
lane 3 lane ID
lane 2 checksum
DAC1208D650
© NXP B.V. 2010. All rights reserved.
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