ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 82

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
The DLIMIT1 and DLIMIT2 registers must be read consecutively and written consecutively. See Section 8.3.
Bits 7 to 0: DPLL Hard Frequency Limit (HARDLIM[7:0]). The full 10-bit HARDLIM[9:0] field spans this register
and DLIMIT2. HARDLIM is an unsigned integer that specifies the hard frequency limit or pull-in/hold-in range of the
T0 DPLL. When frequency limit detection is enabled by setting FLLOL = 1 in the
frequency exceeds the hard limit the DPLL declares loss-of-lock. The hard frequency limit in ppm is
rHARDLIM[9:0] x 0.0782. The default value is normally r9.2ppm. If external reference switching mode is enabled
during reset (see Section 7.6.5), the default value is configured to r79.794ppm (3FFh). See Section 7.7.6.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 1 to 0: DPLL Hard Frequency Limit (HARDLIM[9:8]). See the
________________________________________________________________________________________ DS3104-SE
Bit 7
Bit 7
—
0
0
Bit 6
Bit 6
—
1
0
DLIMIT1
DPLL Frequency Limit Register 1
41h
DLIMIT2
DPLL Frequency Limit Register 1
42h
Bit 5
Bit 5
—
1
0
Bit 4
Bit 4
—
1
0
HARDLIM[7:0]
Bit 3
Bit 3
—
DLIMIT1
0
0
register description.
Bit 2
Bit 2
—
1
0
DLIMIT3
Bit 1
Bit 1
register, if the DPLL
HARDLIM[9:8]
1
0
Bit 0
Bit 0
0
0
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