ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 45

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

________________________________________________________________________________________ DS3104-SE
7.8.2.5 Custom Output Frequencies
In addition to the many standard frequencies available in the device, any of the seven output DFS blocks can be
configured to generate a custom frequency. Possible custom frequencies include any multiple of 2kHz up to
77.76MHz and any multiple of 8kHz up to 311.04MHz. (An APLL must be used to achieve frequencies above
77.76MHz.) Any of the programmable output clocks can be configured to output the custom frequency or
submultiples thereof. Contact the factory at
[e-mail]
for help with custom frequencies.
7.9
Frame and Multiframe Alignment
In addition to receiving and locking to clocks such as 19.44MHz from system timing cards, the DS3104-SE can also
receive and align its outputs to 2kHz multiframe sync or 8kHz frame sync signals from system timing cards. In this
mode of operation, both a higher speed clock (such as 6.48MHz or 19.44MHz) and a frame (or multiframe) sync
signal from each timing card are passed to the line cards. The higher speed clock from each timing card is
connected to a regular input clock pin on the DS3104-SE, such as IC3 or IC4, while the frame sync signal is
connected to a SYNCn input pin on the DS3104-SE, such as SYNC1 or SYNC2. The DS3104-SE locks to the
higher speed clock from one of the timing cards and samples the frame sync signal on the associated SYNCn pin.
The DS3104-SE then uses the SYNCn signal to falling-edge align some or all of the output clocks. Only the falling
edge of the SYNCn signal has significance. A 4kHz or 8kHz clock can also be used on the SYNCn pins without any
changes to the register configuration, but only output clocks of 8kHz and above are aligned in this case. Phase
build-out should be disabled (PBOEN = 0 in MCR10) when using SYNCn signals.
When FSCR3.SOURCE! = 11XX, the frame sync signal can only come from the SYNC1 pin. When
FSCR3.SOURCE = 11XX, the frame sync signal comes from one of SYNC1, SYNC2, or SYNC3. See Section
7.9.3.
7.9.1 Sampling
By default the SYNCn signal is first sampled on the rising edge of the selected reference. This gives the most
margin, given that the SYNCn signal is falling-edge aligned with the selected reference since both come from the
same timing card. The expected timing of the SYNCn signal with respect to the sampling clock can be adjusted
from 0.5 cycles early to 1 cycle late using the FSCR2:PHASEn[1:0] field.
7.9.2 Resampling
The SYNCn signal is then resampled by an internal clock derived from the T0 DPLL. The resampling resolution is a
function of the frequency of the selected reference and FSCR2:OCN. When OCN = 0, the resampling resolution is
6.48MHz, which gives the highest sampling margin and also aligns clocks at 6.48MHz and multiples thereof. When
OCN = 1, if the selected reference is 19.44MHz the resampling resolution is 19.44MHz. If the selected reference is
38.88 MHz the resampling resolution is 38.88MHz. The selected reference must be either 19.44MHz or 38.88MHz.
7.9.3 Enable
The SYNCn signal is only allowed to align output clocks if the T0 DPLL is locked and the SYNCn signal is enabled
and qualified.
When FSCR3:SOURCE[3:0]! = 11XX, external frame sync on the SYNC1 pin can be enabled automatically or
manually. When MCR3:AEFSEN = 1, external frame sync is enabled automatically when EFSEN = 1 and the T0
DPLL is locked to the input clock specified by FSCR3:SOURCE[3:0]. When AEFSEN = 0, external frame sync is
enabled manually when MCR3:EFSEN = 1 and disabled when EFSEN = 0. In manual mode when EFSEN = 1,
FSCR3:SOURCE[3:0] is ignored and external frame sync is always enabled regardless of which input clock is the
selected reference.
When FSCR3:SOURCE[3:0] = 11XX, external frame sync from the SYNCn pins can be enabled when EFSEN = 1
and the associated input clock becomes the selected reference. MCR3:AEFSEN can be used to automatically
disable EFSEN when the selected reference changes. See Section 7.9.7.
45