ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 38

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

7.8.2.1 T0 and T4 DPLL Details
See
synthesize internal clocks from which the output and feedback clocks are derived. The T4 DPLL only has a single
DFS output clock signal for both the output clocks and the feedback clock, whereas there are two DFS output clock
signals in the T0 DPLL, one for the output clocks and one for the feedback clock.
In the T0 DPLL the feedback clock signal output handles phase build-out or any phase offset configured in the
OFFSET
may have a phase offset. The T0 and T4 feedback DFS blocks are always connected to the T0 forward DFS and
the T4 forward DFS, respectively. The feedback DFS blocks synthesize the appropriate locking frequencies for use
by the phase-frequency detectors (PFDs). See Section 7.4.2.
7.8.2.2 Output DFS and APLL Details
See
blocks, and three APLL DFS blocks. Four of the DFS blocks can be connected to either the T0 DPLL or the T4
DPLL, three are always connected to the T0 DPLL. The T0 APLL, the T0 APLL2 and the T4 APLL (and their output
dividers) get their frequency references from three associated APLL DFS blocks. All of the output DFS blocks are
connected to the T0 DPLL when MCR4:LKT4T0 = 1.
The 2K8K DFS and FSYNC DFS blocks generate both 2kHz and 8kHz signals which have about 1ns pk-pk jitter.
The FSYNC (8kHz) and MFSYNC(2 kHz) signals come from the FSYNC DFS block, which is always connected to
the T0 DPLL when not in independent mode (FSCR2:INDEP = 1). The 2kHz and 8kHz signals available on output
clocks OC1 to OC7 come from the 2K8K DFS, which can be connected to either the T0 DPLL or the T4 DPLL
depending on FSCR1:2K8KSRC and MCR4:LKT4T0.
The DIG1 DFS can generate an NxDS1 or NxE1 signal with about 1ns pk-pk jitter. The DIG2 DFS can generate an
NxDS1, NxE1, 6.312MHz, 10MHz, or Nx19.44MHz clock with approximately 1ns pk-pk jitter. Each DIG12 DFS can
be connected to either the T0 DPLL or the T4 DPLL using MCR7:DIG1SRC or MCR7:DIG2SRC and
MCR4:LKT4T0. The frequency of the DIG1 clock is configured by the DIG1SS bit in
in MCR7. The frequency of the DIG2 clock is configured by the DIG2AF and DIG2SS bits in
DIG2F[1:0] field in MCR7. DIG1 and DIG2 can be independently configured for any of the frequencies shown in
Table 7-7
The APLL DFS blocks and their associated output APLLs and output dividers can generate many different
frequencies. The T0 APLL DFS and the T0 APLL2 DFS are always connected to the T0 DPLL. The T4 APLL DFS
can be connected to either the T0 DPLL or the T4 DPLL depending on T0CR1:T4APT0 and MCR4:LKT4T0. The
T0 APLL frequencies that can be generated are listed in
312.500MHz. The T4 APLL frequencies that can be generated are listed in
can be generated from the APLL circuits are listed in
The T4 APLL is disabled and powered down when T4CR1:T4FREQ = 0000 and T0CR1:T4APT0 = 0. In this mode
all outputs connected to the T4 APLL are driven low.
Together the T0 APLL, T0 APLL2 and T4 APLL can simultaneously generate SONET/SDH clock rates, Gigabit
Ethernet clock rates (e.g., 125MHz) and 10G Ethernet clock rates (e.g., 156.25MHz), all locked to the same
selected reference. This capability supports mixed SONET/SDH and Synchronous Ethernet line cards.
________________________________________________________________________________________ DS3104-SE
Figure
Figure
registers. Thus the T0 DPLL output clock signals and the feedback clock signal are frequency locked but
and
7-1. The T0 and T4 forward DFS blocks use the 204.8MHz master clock and DFS technology to
7-1. The output clock frequencies are determined by two 2kHz/8kHz DFS blocks, two DIG12 DFS
Table
7-8, respectively.
Table
7-9.
Table
7-10. The T0 APLL2 frequency is always
Table
7-12. The output frequencies that
MCR6
and the DIG1F[1:0] field
MCR6
and the
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