ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 59

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Frame Sync Input Monitor Alarm (FSMON). This latched status bit is set to 1 when OPSTATE:FSMON
transitions from 0 to 1. FSMON is cleared when written with a 1. When FSMON is set it can cause an interrupt
request on the INTREQ pin if the FSMON interrupt enable bit is set in the
Bit 6: T4 DPLL Lock Status Change (T4LOCK). This latched status bit is set to 1 when the lock status of the T4
DPLL (OPSTATE:T4LOCK) changes (becomes locked when previously unlocked or becomes unlocked when
previously locked). T4LOCK is cleared when written with a 1 and not set again until the T4 lock status changes
again. When T4LOCK is set it can cause an interrupt request on the INTREQ pin if the T4LOCK interrupt enable bit
is set in the
Bit 4: T4 No Valid Inputs Alarm (T4NOIN). This latched status bit is set to 1 when the T4 DPLL has no valid
inputs available. T4NOIN is cleared when written with a 1 unless the T4 DPLL still has no valid inputs available.
When T4NOIN is set it can cause an interrupt request on the INTREQ pin if the T4NOIN interrupt enable bit is set
in the
________________________________________________________________________________________ DS3104-SE
IER3
register. See Section 7.5.
IER3
FSMON
Bit 7
register. See Section 7.7.6.
0
T4LOCK
Bit 6
1
MSR3
Master Status Register 3
08h
Bit 5
—
0
T4NOIN
Bit 4
1
Bit 3
—
0
IER3
register. See Section 7.9.
Bit 2
—
0
Bit 1
—
0
Bit 0
—
0
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