ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 47

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Table 7-15. External Frame Sync Source
There are three PHASEn[1:0] (n = 1, 2, 3) select fields in the
SYNC1, PHASE2[1:0] is associated with SYNC2, and PHASE3[1:0] is associated with SYNC3. All three SYNCn
inputs can have their timing adjusted to account for frame sync signal vs. clock signal delay differences in each
path.
When this function is enabled with FSCR3.SOURCE = 11XX, MCR3.AEFSEN, and MCR3.EFSEN, the monitoring
and qualification function described in Section
7.9.8 Other Configuration Options
FSYNC and MFSYNC are always produced from the T0 DPLL. Output clocks OC1 to OC7 can also be configured
as 2kHz or 8kHz outputs, derived from either the T0 DPLL or the T4 DPLL (as specified by the 2K8KSRC bit in
FSCR1). If needed, the T4 DPLL can be used as a separate DPLL for the frame sync path by configuring it for a
2kHz input and 2kHz and/or 8kHz frame sync outputs.
7.10
The device presents an SPI interface on the CS, SCLK, SDI, and SDO pins. SPI is a widely used master/slave bus
protocol that allows a master device and one or more slave devices to communicate over a serial bus. The
DS3104-SE is always a slave device. Masters are typically microprocessors, ASICs or FPGAs. Data transfers are
always initiated by the master device, which also generates the SCLK signal. The DS3104-SE receives serial data
on the SDI pin and transmits serial data on the SDO pin. SDO is high impedance except when the DS3104-SE is
transmitting data to the bus master.
Bit Order. When both bit 3 and bit 4 are low at device address 3FFFh, the register address and all data bytes are
transmitted MSB first on both SDI and SDO. When either bit 3 or bit 4 is set to 1 at device address 3FFFh, the
register address and all data bytes are transmitted LSB first on both SDI and SDO. The reset default setting and
Motorola SPI convention is MSB first.
Clock Polarity and Phase. The CPOL pin defines the polarity of SCLK. When CPOL = 0, SCLK is normally low
and pulses high during bus transactions. When CPOL = 1, SCLK is normally high and pulses low during bus
transactions. The CPHA pin sets the phase (active edge) of SCLK. When CPHA = 0, data is latched in on SDI on
the leading edge of the SCLK pulse and updated on SDO on the trailing edge. When CPHA = 1, data is latched in
on SDI on the trailing edge of the SCLK pulse and updated on SDO on the following leading edge. SCLK does not
have to toggle between access, i.e., when CS is high. See
Device Selection. Each SPI device has its own chip-select line. To select the DS3104-SE, pull its CS pin low.
Control Word. After CS is pulled low, the bus master transmits the control word during the first sixteen SCLK
cycles. In MSB-first mode the control word has the form:
________________________________________________________________________________________ DS3104-SE
SYNCSRC[2:0]
0XX
1X0
10X
1X1
11X
Microprocessor Interface
R/W A13 A12 A11 A10 A9 A8 A7
REFERENCE
SELECTED
IC3 or IC5
IC4 or IC6
IC9 or IC2
IC3
IC4
IC9
IC5
IC6
IC2
EXTERNAL FRAME
7.9.4
SYNC SOURCE
SYNC1
SYNC2
SYNC3
SYNC1
SYNC2
SYNC3
SYNC1
SYNC2
SYNC3
is only performed on the selected SYNCn input pin.
Figure
A6 A5 A4 A3 A2 A1 A0 BURST
FSCR2
7-5.
register. PHASE1[1:0] is associated with
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