ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 107

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
The OFFSET1 and OFFSET2 registers must be read consecutively and written consecutively. See Section 8.3.
Bits 7 to 0: Phase Offset (OFFSET[7:0]). The full 16-bit OFFSET[15:0] field spans this register and the
register. OFFSET is a two’s-complement signed integer that specifies the desired phase offset between the output
clocks and the selected input reference. The phase offset in picoseconds is equal to OFFSET[15:0] x
actual_internal_clock_period / 2
offset equation simplifies to OFFSET[15:0] x 6.279ps. If, however, the DPLL is locked to a reference whose
frequency is +1ppm from ideal, for example, then the actual internal clock period is 1ppm shorter and the phase
offset is 1ppm smaller. When the OFFSET field is written, the phase of the output clocks is automatically ramped to
the new offset value to avoid loss of synchronization. To adjust the phase offset without changing the phase of the
output clocks, use the recalibration process enabled by FSCR3:RECAL. The OFFSET field is ignored when phase
build-out is enabled (PBOEN = 1 in the
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 0: Phase Offset (OFFSET[15:8]). See the
________________________________________________________________________________________ DS3104-SE
Bit 7
Bit 7
0
0
Bit 6
Bit 6
0
0
11
OFFSET1
Phase Offset Register 1
70h
OFFSET2
Phase Offset Register 2
71h
. If the internal clock is at its nominal frequency of 77.76MHz then the phase
MCR10
Bit 5
Bit 5
0
0
register) and when the DPLL is not locked. See Section 7.7.8.
OFFSET1
Bit 4
Bit 4
OFFSET[15:8]
0
0
OFFSET[7:0]
register description.
Bit 3
Bit 3
0
0
Bit 2
Bit 2
0
0
Bit 1
Bit 1
0
0
OFFSET2
Bit 0
Bit 0
0
0
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