ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 73

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 3 to 0: T0 DPLL Force Selected Reference (T0FORCE[3:0]). This field provides a way to force a specified
input clock to be the selected reference for the T0 DPLL. Internally this is accomplished by forcing the clock to have
the highest priority (as specified in PTAB1:REF1). In revertive mode (MCR3:REVERT = 1) the forced clock
automatically becomes the selected reference (as specified in PTAB1:SELREF) as well. In nonrevertive mode the
forced clock only becomes the selected reference when the existing selected reference is invalidated or made
unavailable for selection.
When a reference is forced, the activity monitor for that input and the T0 DPLL’s loss-of-lock timeout logic all
continue to operate and affect the relevant ISR,
declared invalid the T0 DPLL is not allowed to switch to another input clock. The T0 DPLL continues to respond to
the fast activity monitor, transitioning to mini-holdover in response to short-term events and to full holdover in
response to longer events. See Section 7.6.3.
________________________________________________________________________________________ DS3104-SE
0000 = Automatic source selection (normal operation)
0001 = Force to IC1
0010 = Force to IC2
0011 = Force to IC3
0100 = Force to IC4
0101 = Force to IC5
0110 = Force to IC6
0111 = {unused value}
1000 = Force to IC8
1001 = Force to IC9
1010 to 1110 = {unused values}
1111 = Automatic source selection (normal operation)
Bit 7
—
0
Bit 6
—
0
MCR2
Master Configuration Register 2
33h
Bit 5
—
0
VALSR
Bit 4
—
0
and
MSR
Bit 3
register bits. However, when the reference is
1
Bit 2
T0FORCE[3:0]
1
Bit 1
1
Bit 0
1
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