ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 48

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

where A[13:0] is the register address, R/W is the data direction bit (1 = read, 0 = write), and BURST is the burst bit
(1 = burst access, 0 = single-byte access). In LSB-first mode the order of the 14 address bits is reversed. In the
discussion that follows, a control word with R/W = 1 is a read control word, while a control word with R/W = 0 is a
write control word.
Single-Byte Writes. See
= 0 followed by the data byte to be written. The bus master then terminates the transaction by pulling CS high.
Single-Byte Reads. See
= 0. The DS3104-SE then responds with the requested data byte. The bus master then terminates the transaction
by pulling CS high.
Burst Writes. See
followed by the first data byte to be written. The DS3104-SE receives the first data byte on SDI, writes it to the
specified register, increments its internal address register, and prepares to receive the next data byte. If the master
continues to transmit, the DS3104-SE continues to write the data received and increment its address counter. After
the address counter reaches 3FFFh it rolls over to address 0000h and continues to increment.
Burst Reads. See
The DS3104-SE then responds with the requested data byte on SDO, increments its address counter, and
prefetches the next data byte. If the bus master continues to demand data, the DS3104-SE continues to provide
the data on SDO, increment its address counter, and prefetch the following byte. After the address counter reaches
3FFFh it rolls over to address 0000h and continues to increment.
Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by
pulling CS high. In response to early terminations, the DS3104-SE resets its SPI interface logic and waits for the
start of the next transaction. If a write transaction is terminated prior to the SCLK edge that latches the LSB of a
data byte, the data byte is not written.
Design Option: Wiring SDI and SDO Together. Because communication between the bus master and the
DS3104-SE is half-duplex, the SDI and SDO pins can be wired together externally to reduce wire count. To support
this option, the bus master must not drive the SDI/SDO line when the DS3104-SE is transmitting.
AC Timing. See
________________________________________________________________________________________ DS3104-SE
Table 10-10
Figure
Figure
Figure
Figure
7-6. After CS goes low, the bus master transmits a read control word with BURST = 1.
7-6. After CS goes low, the bus master transmits a write control word with BURST = 1
and
7-6. After CS goes low, the bus master transmits a write control word with BURST
7-6. After CS goes low, the bus master transmits a read control word with BURST
Figure 10-4
for AC timing specifications for the SPI interface.
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