ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 44

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

7.8.2.4 FSYNC and MFSYNC Configuration
The FSYNC output is enabled by setting FSEN = 1 in the
setting MFSEN = 1 in OCR4. When disabled, these pins are driven low.
When 8KPUL = 0 in FSCR1, FSYNC is configured as an 8kHz clock with 50% duty cycle. When 8KPUL = 1,
FSYNC is an 8kHz frame sync that pulses low once every 125Ps with pulse width equal to one cycle of output
clock OC3. When 8KINV = 1 in FSCR1, the clock or pulse polarity of FSYNC is inverted.
When 2KPUL = 0 in FSCR1, MFSYNC is configured as an 2kHz clock with 50% duty cycle. When 2KPUL = 1,
MFSYNC is a 2kHz frame sync that pulses low once every 500Ps with pulse width equal to one cycle of output
clock OC3. When 2KINV = 1 in FSCR1, the clock or pulse polarity f MFSYNC is inverted.
If either 8KPUL = 1 or 2KPUL = 1, then output clock OC3 must be generated from the T0 DPLL and must be
configured for a frequency of 1.544MHz or higher or the FSYNC/MFSYNC pulses may not be generated correctly.
Figure 7-4
have an identical effect on MFSYNC.
Figure 7-4. FSYNC 8kHz Options
________________________________________________________________________________________ DS3104-SE
122.880
125.000
131.072
137.472
148.224
155.520
156.250
160.000
178.944
250.000
274.944
311.040
312.500
FSYNC, 8KPUL=0, 8KINV=0
FSYNC, 8KPUL=0, 8KINV=1
FSYNC, 8KPUL=1, 8KINV=0
FSYNC, 8KPUL=1, 8KINV=1
shows how the 8KPUL and 8KINV control bits affect the FSYNC output. The 2KPUL and 2KINV bits
FREQUENCY (MHz)
OC6, OC7 only
not OC1-OC3 from T0 APLL
not OC1, OC2 from T4 APLL
not OC1-OC3 from T0 APLL
OC6, OC7 only from T4 APLL
OC6, OC7 only
not OC1-OC3 from T0 APLL
OC6, OC7 only from T4 APLL
not OC1-OC3 from T0 APLL
not OC1, OC2 from T4 APLL
OC4-OC7 only from T0 APLL2
OC6, OC7 only
OC6, OC7 only
OC4-OC7 only
OC6, OC7 only
OC4-OC7 only
OC4-OC7 only from T0 APLL2
OC3 output clock
GbE y 16
GbE y 16
T0 APLL
24 x DS1
T0FREQ
16 x E1
77.76
77.76
OCR4
GbE y 16
24 x DS1
16 x E1
T4FT0
register, while the MFSYNC output is enabled by
T4 APLL
GbE y 16
3 x 10.24
24 x DS1
T4FREQ
16 x E1
2 x E3
4 x 10
77.76
DS3
OFREQn
APLL/1
APLL/2
APLL/1
APLL/2
APLL/1
APLL/2
APLL/2
APLL/1
APLL/1
APLL/1
APLL/1
APLL/2
RMS
(ps)
50
50
50
50
50
60
50
50
50
50
50
50
JITTER
(TYP)
pk-pk
0.50
0.50
0.50
0.50
0.50
0.50
0.50
0.50
0.50
0.50
0.50
(ns)
0.6
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