ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 46

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

________________________________________________________________________________________ DS3104-SE
7.9.4 Qualification
The SYNCn signal is qualified when it has consistent phase and correct frequency. Specifically, it is qualified when
its significant edge has been found at exact 2kHz boundaries (when resampled as described above) for 64 cycles
in a row. It is disqualified when one significant edge is not found at the 2kHz boundary. If there is no SYNCn signal
or a bad SYNCn signal, and external frame sync is enabled, the SYNCn signal will never get qualified and the 2kHz
output will simply free-run at its current 2kHz alignment.
7.9.5 Output Clock Alignment
When the T0 DPLL is locked, external frame sync is enabled and the SYNCn signal is qualified, the SYNCn signal
can be used to falling-edge align the T0 DPLL derived output clocks. Output clocks FSYNC and MFSYNC share a
2kHz alignment generator, while the rest of the T0 DPLL derived output clocks share a second 2kHz alignment
generator. When external frame sync is not enabled or the SYNCn signal is not qualified, these 2Hz alignment
generators free-run with their existing 2kHz alignments. When external frame sync is enabled and the SYNCn
signal is qualified, the FSYNC/MFSYNC 2kHz alignment generator is always synchronized by SYNCn, and
therefore FSYNC and MFSYNC are always falling-edge aligned with SYNCn. When FSCR2:INDEP = 0, the T0
DPLL 2kHz alignment generator is also synchronized with the FSYNC/MFSYNC 2kHz alignment generator to
falling-edge align all T0-derived output clocks with SYNCn. When INDEP = 1, the T0 DPLL 2-kHz alignment
generator is not synchronized with the FSYNC/MFSYNC 2kHz alignment generator and continues to free-run with
its existing 2kHz alignment. This avoids any disturbance on the T0 DPLL derived output clocks when SYNCn has a
change of phase position.
7.9.6 Frame Sync Monitor
The frame sync monitor signal OPSTATE:FSMON operates in two modes, depending on the setting of the enable
bit (MCR3:EFSEN).
When EFSEN = 1 (external frame sync enabled) the OPSTATE:FSMON bit is set when SYNCn is not qualified and
cleared when SYNCn is qualified. If SYNCn is disqualified then both 2kHz alignment generators are immediately
disconnected from SYNCn to avoid phase movement on the T0-derived outputs clocks. When OPSTATE:FSMON
is set, the latched status bit MSR3:FSMON is also set, which can cause an interrupt if enabled in the
IER3
register.
If SYNCn immediately stabilizes at a new phase and proper frequency, then it is requalified after 64 2kHz cycles
(nominally 32ms). Unless system software intervenes, after SYNCn is requalified the 2kHz alignment generators
will synchronize with SYNCn’s new phase alignment, causing a sudden phase movement on the output clocks.
System software can avoid this sudden phase movement on the output clocks by responding to the FSMON
interrupt within the 32ms window with appropriate action, which might include disabling external frame sync
(MCR3:EFSEN = 0) to prevent the resynchronization of the 2kHz alignment generators with SYNCn, forcing the T0
DPLL into holdover (MCR1:T0STATE = 010) to avoid affecting the output clocks with any other phase hits, and
possibly even disabling the master timing card and promoting the slave timing card to master since the 2kHz signal
from the master should not have such phase movements.
When EFSEN = 0 (external frame sync disabled) OPSTATE:FSMON is set when the negative edge of the re-
sampled SYNCn signal is outside of the window determined by FSCR3:MONLIM relative to the MFSYNC negative
edge (or positive edge if MFSYNC is inverted) and clear when within the window. When OPSTATE:FSMON is set,
the latched status bit MSR3:FSMON is also set, which can cause an interrupt if enabled in the
IER3
register.
7.9.7 SYNCn Pins
The external frame sync signal can be automatically selected from one to three separate SYNC[1:3] pins
depending on the setting of FSCR1:SYNCSRC[2:0] and which input clock is the T0 DPLL selected reference. If no
associated input pin is selected as the T0 DPLL input reference, the internal SYNCn signal is inactive and will not
be qualified. This function is enabled by setting FSCR3.SOURCE = 11XX.
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