ds3104-se Maxim Integrated Products, Inc., ds3104-se Datasheet - Page 58

• Manufacturer Part Number: ds3104-se
• Description: Line Card Timing Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 and 5 to 0: Input Clock Status Change (IC8 and IC[6:1]). Each of these latched status bits is set to 1
when the corresponding
and not set again until the
cause an interrupt request on the INTREQ pin if the corresponding interrupt enable bit is set in the
See Section
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: T0 DPLL State Change (STATE). This latched status bit is set to 1 when the operating state of the T0 DPLL
changes. STATE is cleared when written with a 1 and not set again until the operating state changes again. When
STATE is set it can cause an interrupt request on the INTREQ pin if the STATE interrupt enable bit is set in the
IER2
Section 7.7.1.
Bit 6: Selected Reference Failed (SRFAIL). This latched status bit is set to 1 when the selected reference to the
T0 DPLL fails, (i.e., no clock edges in two UI). SRFAIL is cleared when written with a 1. When SRFAIL is set it can
cause an interrupt request on the INTREQ pin if the SRFAIL interrupt enable bit is set in the
is not set in free-run mode or holdover mode. See Section 7.5.3.
Bit 0: Input Clock Status Change (IC9). This latched status bit is set to 1 when the corresponding
bit changes state (set or cleared). Each bit is cleared when written with a 1 and not set again until the
changes state again. When this latched status bit is set it can cause an interrupt request on the INTREQ pin if the
corresponding interrupt enable bit is set in the
criteria.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 2 to 0: Current DPLL Frequency (FREQ[18:16]). See the
________________________________________________________________________________________ DS3104-SE
register. The current operating state can be read from the T0STATE field of the
7.5
STATE
Bit 7
for input clock validation/invalidation criteria.
Bit 7
Bit 7
—
IC8
0
0
1
VALSR1
SRFAIL
VALSR1
Bit 6
Bit 6
Bit 6
—
0
0
—
0
MSR1
Master Status Register 1
05h
MSR2
Master Status Register 2
06h
FREQ3
Frequency Register 3
07h
status bit changes state (set or cleared). Each bit is cleared when written with a 1
bit changes state again. When one of these latched status bits is set it can
Bit 5
Bit 5
Bit 5
—
—
IC6
0
0
1
IER2
register. See Section
Bit 4
Bit 4
—
—
Bit 4
0
0
IC5
1
FREQ1
Bit 3
Bit 3
Bit 3
—
—
IC4
0
0
1
register description.
7.5
for input clock validation/invalidation
Bit 2
IC3
Bit 2
Bit 2
1
—
0
0
FREQ[18:16]
OPSTATE
IER2
Bit 1
IC2
Bit 1
Bit 1
1
—
0
0
register. SRFAIL
VALSR
IER1
register. See
VALSR2
Bit 0
Bit 0
Bit 0
IC1
IC9
register.
1
1
0
status
58
bit