upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 97

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Notes 1.
2.
3.
4.
CPU clock: f
f
f
XP
R
Before shifting from status 2 to status 3 after reset and STOP are released, check the high-speed
system clock oscillation stabilization time status using the oscillation stabilization time counter status
register (OSTC).
Waiting for the oscillation stabilization time is not required when the external RC oscillation clock is
selected as the high-speed system clock by the option byte. Therefore, the CPU clock can be
switched without reading the OSTC value.
When shifting from status 2 to status 1, make sure that MCS is 0.
The watchdog timer operates using the internal oscillation clock even in STOP mode if “Internal
oscillator cannot be stopped” is selected by the option byte. Internal oscillation clock division can be
selected as the count source of 8-bit timer H1 (TMH1), so clear the watchdog timer using the TMH1
interrupt request before watchdog timer overflow. If this processing is not performed, an internal
reset signal is generated at watchdog timer overflow after STOP instruction execution.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
: Oscillating
: Oscillating
Status 3
(2) When “Internal oscillator cannot be stopped” is selected by option byte
XP
instruction
Interrupt
STOP
MCM0 = 1
Figure 5-13. Status Transition Diagram (2/2)
MCM0 = 0
Interrupt
HALT
instruction
CHAPTER 5 CLOCK GENERATOR
Note 1
User’s Manual U16846EJ3V0UD
instruction
Interrupt
STOP
f
CPU clock: f
f
XP
R
STOP
: Oscillating
: Oscillating
Status 2
HALT
Note 3
HALT
instruction
Interrupt
R
Interrupt
instruction
MSTOP = 1
MSTOP = 0
STOP
Reset release
HALT instruction
Interrupt
Note 2
f
XP
: Oscillation stopped
CPU clock: f
f
Reset
R
: Oscillating
Status 1
Note 4
R
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