upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 424

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

424
8-bit timers
H0, H1
(TMH0,
TMH1)
Watchdog
timer
Function
Details of Function
CMP0n: 8-bit
timer H compare
register 0n
CMP1n: 8-bit
timer H compare
register 1n
TMHMD0: 8-bit
timer H mode
register 0
TMHMD1: 8-bit
timer H mode
register 1
PWM output
WDTM: Watchdog
timer mode
register
WDTE: Watchdog
timer enable
register
CMP0n cannot be rewritten during timer count operation.
In the PWM output mode be sure to set CMP1n when starting the timer count operation
(TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be sure to set
again even if setting the same value to CMP1n).
When the internal oscillation clock is selected as the clock to be supplied to the CPU, the
clock of the internal oscillator is divided and supplied as the count clock. If the count clock
is the internal oscillation clock, the operation of 8-bit timer H0 is not guaranteed.
When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited.
In the PWM output mode, be sure to set 8-bit timer H compare register 10 (CMP10) when
starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped
(TMHE0 = 0) (be sure to set again even if setting the same value to CMP10).
When the internal oscillation clock is selected as the clock to be supplied to the CPU, the
clock of the internal oscillator is divided and supplied as the count clock. If the count clock
is the internal oscillation clock, the operation of 8-bit timer H1 is not guaranteed (except
when CKS12, CKS11, CKS10 = 1, 0, 1 (f
When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited.
In the PWM output mode, be sure to set 8-bit timer H compare register 11 (CMP11) when
starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped
(TMHE1 = 0) (be sure to set again even if setting the same value to CMP11).
In PWM output mode, three operation clocks (signal selected using the CKSn2 to CKSn0
bits of the TMHMDn register) are required to transfer the CMP1n register value after
rewriting the register.
Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1)
after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if
setting the same value to the CMP1n register).
Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N)
are within the following range.
00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
If data is written to WDTM, a wait cycle is generated. For details, see CHAPTER 27
CAUTIONS FOR WAIT.
Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when “Internal oscillator cannot be stopped”
is selected by the option byte, other values are ignored).
After reset is released, WDTM can be written only once by an 8-bit memory manipulation
instruction. If writing is attempted a second time, an internal reset signal is generated. If
the source clock to the watchdog timer is stopped, however, an internal reset signal is
generated when the source clock to the watchdog timer resumes operation.
WDTM cannot be set by a 1-bit memory manipulation instruction.
If “Internal oscillator can be stopped by software” is selected by the option byte and the
watchdog timer is stopped by setting WDCS4 to 1, the watchdog timer does not resume
operation even if WDCS4 is cleared to 0. In addition, the internal reset signal is not
generated.
If a value other than ACH is written to WDTE, an internal reset signal is generated. If the
source clock to the watchdog timer is stopped, however, an internal reset signal is
generated when the source clock to the watchdog timer resumes operation.
If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal is
generated. If the source clock to the watchdog timer is stopped, however, an internal reset
signal is generated when the source clock to the watchdog timer resumes operation.
The value read from WDTE is 9AH (this differs from the written value (ACH)).
APPENDIX D LIST OF CAUTIONS
User’s Manual U16846EJ3V0UD
R
Cautions
/2
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