upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 220

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(4) Permissible baud rate range during reception
220
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
As shown in Figure 11-12, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
Maximum permissible
FL = (Brate)
Minimum permissible
Data frame length
Brate: Baud rate of UART0
k:
FL:
Margin of latch timing: 2 clocks
data frame length
data frame length
using the calculation expression shown below.
of UART0
Set value of BRGC0
1-bit data length
CHAPTER 11 SERIAL INTERFACE UART0 (
−
1
Figure 11-12. Permissible Baud Rate Range During Reception
Latch timing
Start bit
Start bit
Start bit
User’s Manual U16846EJ3V0UD
Bit 0
Bit 0
FL
Bit 0
Bit 1
Bit 1
Bit 1
1 data frame (11 × FL)
PD78F0102H AND 78F0103H ONLY)
FLmin
FLmax
Bit 7
Bit 7
Bit 7
Parity bit
Parity bit
Parity bit
Stop bit
Stop bit
Stop bit