upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 175

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(2) Watchdog timer enable register (WDTE)
Internal
Reset Signal
Generation Cause
Watchdog timer
overflows
Write to WDTM for the
second time
Write other than “ACH”
to WDTE
Access WDTE by 1-bit
memory manipulation
instruction
Address: FF99H
Symbol
WDTE
Writing ACH to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to 9AH.
The relationship between the watchdog timer operation and the internal reset signal generated by the watchdog
timer is shown below.
Watchdog Timer
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. If
Operation
7
After reset: 9AH
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
3. The value read from WDTE is 9AH (this differs from the written value (ACH)).
Table 9-4. Relationship Between Watchdog Timer Operation and
Internal reset signal is
generated.
Internal reset signal is
generated.
Internal reset signal is
generated.
Figure 9-3. Format of Watchdog Timer Enable Register (WDTE)
Cannot Be Stopped by
Software” Is Selected
the source clock to the watchdog timer is stopped, however, an internal reset signal
is generated when the source clock to the watchdog timer resumes operation.
signal is generated. If the source clock to the watchdog timer is stopped, however,
an internal reset signal is generated when the source clock to the watchdog timer
resumes operation.
(Watchdog Timer Is
Always Operating)
“Internal Oscillator
by Option Byte
6
Internal Reset Signal Generated by Watchdog Timer
R/W
5
CHAPTER 9 WATCHDOG TIMER
User’s Manual U16846EJ3V0UD
Internal reset signal is
generated.
Internal reset signal is
generated.
Internal reset signal is
generated.
“Internal Oscillator Can Be Stopped by Software” Is Selected by Option Byte
Watchdog Timer Is
4
Operating
3
Internal reset signal is
not generated and the
watchdog timer does
not resume operation.
Internal reset signal is
not generated.
WDCS4 Is Set to 1
2
−
Watchdog Timer Stopped
1
Internal reset signal is
generated when the
source clock to the
watchdog timer
resumes operation.
Internal reset signal is
generated when the
source clock to the
watchdog timer
resumes operation.
Watchdog Timer Is
0
Source Clock to
Stopped
−
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